diff options
Diffstat (limited to 'src/devices/pic/xml_data/18F2320.xml')
| -rw-r--r-- | src/devices/pic/xml_data/18F2320.xml | 271 |
1 files changed, 271 insertions, 0 deletions
diff --git a/src/devices/pic/xml_data/18F2320.xml b/src/devices/pic/xml_data/18F2320.xml new file mode 100644 index 0000000..80e8250 --- /dev/null +++ b/src/devices/pic/xml_data/18F2320.xml @@ -0,0 +1,271 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!--************************************************************************--> +<!--* Copyright (C) 2005-2007 Nicolas Hadacek <hadacek@kde.org> *--> +<!--* *--> +<!--* This program is free software; you can redistribute it and/or modify *--> +<!--* it under the terms of the GNU General Public License as published by *--> +<!--* the Free Software Foundation; either version 2 of the License, or *--> +<!--* (at your option) any later version. *--> +<!--************************************************************************--> +<device name="18F2320" document="010267" status="IP" memory_technology="FLASH" self_write="yes" architecture="18F" id="0x0500" > + +<!--* Checksums ************************************************************--> + <checksums> + <checksum protected_blocks="0" bchecksum="0xE412" cchecksum="0xE368" /> + <checksum protected_blocks="1" bchecksum="0xE5E7" cchecksum="0xE59C" /> + <checksum protected_blocks="2" bchecksum="0xEBE6" cchecksum="0xEB9B" /> + <checksum protected_blocks="3" bchecksum="0xF3E4" cchecksum="0xF399" /> + <checksum protected_blocks="4" bchecksum="0xFBE0" cchecksum="0xFB95" /> + <checksum protected_blocks="5" bchecksum="0x03D8" cchecksum="0x03E2" /> + </checksums> + +<!--* Operating characteristics ********************************************--> + <frequency_range name="industrial" > + <frequency start="0" end="40" vdd_min="4.2" vdd_max="5.5" /> + </frequency_range> + <frequency_range name="industrial" special="low_power" > + <frequency start="0" end="4" vdd_min="2" vdd_max="5.5" /> + <frequency start="4" end="40" vdd_min="2" vdd_max="5.5" vdd_min_end="4.2" /> + </frequency_range> + <frequency_range name="extended" > + <frequency start="0" end="25" vdd_min="4.2" vdd_max="5.5" /> + </frequency_range> + + <voltages name="vpp" min="9" max="13.25" nominal="13" /> + <voltages name="vdd_prog" min="4.5" max="5.5" nominal="5" /> + <voltages name="vdd_prog_write" min="2" max="5.5" nominal="5" /> + +<!--* Memory ***************************************************************--> + <memory name="code" start="0x000000" end="0x001FFF" word_write_align="4" word_erase_align="32" /> + <memory name="user_ids" start="0x200000" end="0x200007" rmask="0x0F" /> + <memory name="device_id" start="0x3FFFFE" end="0x3FFFFF" /> + <memory name="config" start="0x300000" end="0x30000D" /> + <memory name="eeprom" start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" /> + <memory name="debug_vector" start="0x200028" end="0x200037" /> + +<!--* Configuration bits ***************************************************--> + <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" /> + + <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0xCF" > + <mask name="FOSC" value="0x0F" > + <value value="0x00" name="LP" cname="_LP_OSC" /> + <value value="0x01" name="XT" cname="_XT_OSC" /> + <value value="0x02" name="HS" cname="_HS_OSC" /> + <value value="0x03" name="invalid" /> + <value value="0x04" name="EC_CLKOUT" cname="_EC_OSC" /> + <value value="0x05" name="EC_IO" cname="_ECIO_OSC" /> + <value value="0x06" name="H4" cname="_HSPLL_OSC" /> + <value value="0x07" name="EXTRC_IO" cname="_RCIO_OSC" /> + <value value="0x08" name="INTRC_IO" cname="_INTIO2_OSC" /> + <value value="0x09" name="INTRC_CLKOUT" cname="_INTIO1_OSC" /> + <value value="default" name="EXTRC_CLKOUT" cname="_RC_OSC" /> + </mask> + <mask name="FCMEN" value="0x40" > + <value value="0x00" name="Off" cname="_FSCM_OFF" /> + <value value="0x40" name="On" cname="_FSCM_ON" /> + </mask> + <mask name="IESO" value="0x80" > + <value value="0x00" name="Off" cname="_IESO_OFF" /> + <value value="0x80" name="On" cname="_IESO_ON" /> + </mask> + </config> + + <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" > + <mask name="PWRTE" value="0x01" > + <value value="0x00" name="On" cname="_PWRT_ON" /> + <value value="0x01" name="Off" cname="_PWRT_OFF" /> + </mask> + <mask name="BODEN" value="0x02" > + <value value="0x00" name="Off" cname="_BOR_OFF" /> + <value value="0x02" name="On" cname="_BOR_ON" /> + </mask> + <mask name="BORV" value="0x0C" > + <value value="0x00" name="4.5" cname="_BORV_45" /> + <value value="0x04" name="4.2" cname="_BORV_42" /> + <value value="0x08" name="2.7" cname="_BORV_27" /> + <value value="0x0C" name="2.0" cname="_BORV_20" /> + </mask> + </config> + + <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" > + <mask name="WDT" value="0x01" > + <value value="0x00" name="Off" cname="_WDT_OFF" /> + <value value="0x01" name="On" cname="_WDT_ON" /> + </mask> + <mask name="WDTPS" value="0x1E" > + <value value="0x00" name="1:1" cname="_WDTPS_1" /> + <value value="0x02" name="1:2" cname="_WDTPS_2" /> + <value value="0x04" name="1:4" cname="_WDTPS_4" /> + <value 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/> + <value value="0x01" name="RC1" cname="_CCP2MX_C1" ecnames="_CCP2MX_ON" /> + </mask> + <mask name="PBADEN" value="0x02" > + <value value="0x00" name="digital" cname="_PBAD_DIG" /> + <value value="0x02" name="analog" cname="_PBAD_ANA" /> + </mask> + <mask name="MCLRE" value="0x80" > + <value value="0x00" name="Internal" cname="_MCLRE_OFF" /> + <value value="0x80" name="External" cname="_MCLRE_ON" /> + </mask> + </config> + + <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" > + <mask name="STVREN" value="0x01" > + <value value="0x00" name="Off" cname="_STVR_OFF" /> + <value value="0x01" name="On" cname="_STVR_ON" /> + </mask> + <mask name="LVP" value="0x04" > + <value value="0x00" name="Off" cname="_LVP_OFF" /> + <value value="0x04" name="On" cname="_LVP_ON" /> + </mask> + <mask name="DEBUG" value="0x80" > + <value value="0x00" name="On" cname="_DEBUG_ON" /> + <value value="0x80" name="Off" cname="_DEBUG_OFF" /> + </mask> + </config> + + <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" /> + + <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" > + <mask name="CP_0" value="0x01" > + <value value="0x00" name="0200:07FF" cname="_CP0_ON" /> + <value value="0x01" name="Off" cname="_CP0_OFF" /> + </mask> + <mask name="CP_1" value="0x02" > + <value value="0x00" name="0800:0FFF" cname="_CP1_ON" /> + <value value="0x02" name="Off" cname="_CP1_OFF" /> + </mask> + <mask name="CP_2" value="0x04" > + <value value="0x00" name="1000:17FF" cname="_CP2_ON" /> + <value value="0x04" name="Off" cname="_CP2_OFF" /> + </mask> + <mask name="CP_3" value="0x08" > + <value value="0x00" name="1800:1FFF" cname="_CP3_ON" /> + <value value="0x08" name="Off" cname="_CP3_OFF" /> + </mask> + </config> + + <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" > + <mask name="CPB" value="0x40" > + <value value="0x00" name="0000:01FF" cname="_CPB_ON" /> + <value value="0x40" name="Off" cname="_CPB_OFF" /> + </mask> + <mask name="CPD" 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cname="_WRTC_ON" /> + <value value="0x20" name="Off" cname="_WRTC_OFF" /> + </mask> + <mask name="WRTB" value="0x40" > + <value value="0x00" name="0000:01FF" cname="_WRTB_ON" /> + <value value="0x40" name="Off" cname="_WRTB_OFF" /> + </mask> + <mask name="WRTD" value="0x80" > + <value value="0x00" name="All" cname="_WRTD_ON" /> + <value value="0x80" name="Off" cname="_WRTD_OFF" /> + </mask> + </config> + + <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" > + <mask name="EBTR_0" value="0x01" > + <value value="0x00" name="0200:07FF" cname="_EBTR0_ON" /> + <value value="0x01" name="Off" cname="_EBTR0_OFF" /> + </mask> + <mask name="EBTR_1" value="0x02" > + <value value="0x00" name="0800:0FFF" cname="_EBTR1_ON" /> + <value value="0x02" name="Off" cname="_EBTR1_OFF" /> + </mask> + <mask name="EBTR_2" value="0x04" > + <value value="0x00" name="1000:17FF" cname="_EBTR2_ON" /> + <value value="0x04" name="Off" cname="_EBTR2_OFF" /> + </mask> + <mask name="EBTR_3" value="0x08" > + <value value="0x00" name="1800:1FFF" cname="_EBTR3_ON" /> + <value value="0x08" name="Off" cname="_EBTR3_OFF" /> + </mask> + </config> + + <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" > + <mask name="EBTRB" value="0x40" > + <value value="0x00" name="0000:01FF" cname="_EBTRB_ON" /> + <value value="0x40" name="Off" cname="_EBTRB_OFF" /> + </mask> + </config> + +<!--* Packages *************************************************************--> + <package types="sdip soic" nb_pins="28" > + <pin index="1" name="" /> + <pin index="2" name="" /> + <pin index="3" name="" /> + <pin index="4" name="" /> + <pin index="5" name="" /> + <pin index="6" name="" /> + <pin index="7" name="" /> + <pin index="8" name="" /> + <pin index="9" name="" /> + <pin index="10" name="" /> + <pin index="11" name="" /> + <pin index="12" name="" /> + <pin index="13" name="" /> + <pin index="14" name="" /> + <pin index="15" name="" /> + <pin index="16" name="" /> + <pin index="17" name="" /> + <pin index="18" name="" /> + <pin index="19" name="" /> + <pin index="20" name="" /> + <pin index="21" name="" /> + <pin index="22" name="" /> + <pin index="23" name="" /> + <pin index="24" name="" /> + <pin index="25" name="" /> + <pin index="26" name="" /> + <pin index="27" name="" /> + <pin index="28" name="" /> + </package> + +</device> |