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authorMichele Calgaro <michele.calgaro@yahoo.it>2014-01-09 00:24:34 +0100
committerSlávek Banko <slavek.banko@axis.cz>2014-01-09 00:24:34 +0100
commitbf4e405e03859bf383f55715944f4f71bd338c34 (patch)
tree293783d05c079b477b9ef396bbd851ca01714e2d /kate/data/verilog.xml
parentc5189a79b8621b38b53e3cec952d49630e16dd3a (diff)
downloadtdelibs-bf4e405e03859bf383f55715944f4f71bd338c34.tar.gz
tdelibs-bf4e405e03859bf383f55715944f4f71bd338c34.zip
Update kate syntax highlight files
Diffstat (limited to 'kate/data/verilog.xml')
-rw-r--r--kate/data/verilog.xml2
1 files changed, 1 insertions, 1 deletions
diff --git a/kate/data/verilog.xml b/kate/data/verilog.xml
index 12619f2e8..04908146c 100644
--- a/kate/data/verilog.xml
+++ b/kate/data/verilog.xml
@@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE language SYSTEM "language.dtd">
-<language name="Verilog" version="1.09" kateversion="2.4" section="Hardware" extensions="*.v;*.V;*.vl" mimetype="text/x-verilog-src" author="Yevgen Voronenko (ysv22@drexel.edu), Ryan Dalzell (ryan@tullyroan.com)" license="">
+<language name="Verilog" version="1.10" kateversion="2.5" section="Hardware" extensions="*.v;*.V;*.vl" mimetype="text/x-verilog-src" author="Yevgen Voronenko (ysv22@drexel.edu), Ryan Dalzell (ryan@tullyroan.com)" license="">
<highlighting>
<list name="keywords">
<item> macromodule </item>