Added remaining missing Kate xml files

git-svn-id: svn://anonsvn.kde.org/home/kde/branches/trinity/kdelibs@1068844 283d02a7-25f6-0310-bc7c-ecb5cbfe19da

1 files changed, 340 insertions, 280 deletions

diff --git a/kate/data/vhdl.xml b/kate/data/vhdl.xml
index 8dd836cd1..5b1b69494 100644
--- a/kate/data/vhdl.xml
+++ b/kate/data/vhdl.xml
@@ -1,286 +1,346 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!DOCTYPE language SYSTEM "language.dtd">
-<language name="VHDL" version="1.04" kateversion="2.1" section="Hardware" extensions="*.vhdl;*.vhd" mimetype="text/x-vhdl">
-    <highlighting>
-        <list name="keywords">
-            <item> access </item>
-            <item> after </item>
-            <item> alias </item>
-            <item> all </item>
-            <item> assert </item>
-            <item> architecture </item>
-            <item> begin </item>
-            <item> block </item>
-            <item> body </item>
-            <item> buffer </item>
-            <item> bus </item>
-            <item> case </item>
-            <item> component </item>
-            <item> configuration </item>
-            <item> constant </item>
-            <item> disconnect </item>
-            <item> downto </item>
-            <item> else </item>
-            <item> elsif </item>
-            <item> end </item>
-            <item> entity </item>
-            <item> exit </item>
-            <item> file </item>
-            <item> for </item>
-            <item> function </item>
-            <item> generate </item>
-            <item> generic </item>
-            <item> group </item>
-            <item> guarded </item>
-            <item> if </item>
-            <item> impure </item>
-            <item> in </item>
-            <item> inertial </item>
-            <item> inout </item>
-            <item> is </item>
-            <item> label </item>
-            <item> library </item>
-            <item> linkage </item>
-            <item> literal </item>
-            <item> loop </item>
-            <item> map </item>
-            <item> new </item>
-            <item> next </item>
-            <item> null </item>
-            <item> of </item>
-            <item> on </item>
-            <item> open </item>
-            <item> others </item>
-            <item> out </item>
-            <item> package </item>
-            <item> port </item>
-            <item> postponed </item>
-            <item> procedure </item>
-            <item> process </item>
-            <item> pure </item>
-            <item> range </item>
-            <item> record </item>
-            <item> register </item>
-            <item> reject </item>
-            <item> report </item>
-            <item> return </item>
-            <item> select </item>
-            <item> severity </item>
-            <item> signal </item>
-            <item> shared </item>
-            <item> subtype </item>
-            <item> then </item>
-            <item> to </item>
-            <item> transport </item>
-            <item> type </item>
-            <item> unaffected </item>
-            <item> units </item>
-            <item> until </item>
-            <item> use </item>
-            <item> variable </item>
-            <item> wait </item>
-            <item> when </item>
-            <item> while </item>
-            <item> with </item>
-            <item> note </item>
-            <item> warning </item>
-            <item> error </item>
-            <item> failure </item>
-            <item> ACCESS </item>
-            <item> AFTER </item>
-            <item> ALIAS </item>
-            <item> ALL </item>
-            <item> ASSERT </item>
-            <item> ARCHITECTURE </item>
-            <item> BEGIN </item>
-            <item> BLOCK </item>
-            <item> BODY </item>
-            <item> BUFFER </item>
-            <item> BUS </item>
-            <item> CASE </item>
-            <item> COMPONENT </item>
-            <item> CONFIGURATION </item>
-            <item> CONSTANT </item>
-            <item> DISCONNECT </item>
-            <item> DOWNTO </item>
-            <item> ELSE </item>
-            <item> ELSIF </item>
-            <item> END </item>
-            <item> ENTITY </item>
-            <item> EXIT </item>
-            <item> FILE </item>
-            <item> FOR </item>
-            <item> FUNCTION </item>
-            <item> GENERATE </item>
-            <item> GENERIC </item>
-            <item> GROUP </item>
-            <item> GUARDED </item>
-            <item> IF </item>
-            <item> IMPURE </item>
-            <item> IN </item>
-            <item> INERTIAL </item>
-            <item> INOUT </item>
-            <item> IS </item>
-            <item> LABEL </item>
-            <item> LIBRARY </item>
-            <item> LINKAGE </item>
-            <item> LITERAL </item>
-            <item> LOOP </item>
-            <item> MAP </item>
-            <item> NEW </item>
-            <item> NEXT </item>
-            <item> NULL </item>
-            <item> OF </item>
-            <item> ON </item>
-            <item> OPEN </item>
-            <item> OTHERS </item>
-            <item> OUT </item>
-            <item> PACKAGE </item>
-            <item> PORT </item>
-            <item> POSTPONED </item>
-            <item> PROCEDURE </item>
-            <item> PROCESS </item>
-            <item> PURE </item>
-            <item> RANGE </item>
-            <item> RECORD </item>
-            <item> REGISTER </item>
-            <item> REJECT </item>
-            <item> REPORT </item>
-            <item> RETURN </item>
-            <item> SELECT </item>
-            <item> SEVERITY </item>
-            <item> SIGNAL </item>
-            <item> SHARED </item>
-            <item> SUBTYPE </item>
-            <item> THEN </item>
-            <item> TO </item>
-            <item> TRANSPORT </item>
-            <item> TYPE </item>
-            <item> UNAFFECTED </item>
-            <item> UNITS </item>
-            <item> UNTIL </item>
-            <item> USE </item>
-            <item> VARIABLE </item>
-            <item> WAIT </item>
-            <item> WHEN </item>
-            <item> WHILE </item>
-            <item> WITH </item>
-            <item> NOTE </item>
-            <item> WARNING </item>
-            <item> ERROR </item>
-            <item> FAILURE </item>
-            <item> and </item>
-            <item> or </item>
-            <item> xor </item>
-            <item> not </item>
-            <item> AND </item>
-            <item> OR </item>
-            <item> XOR </item>
-            <item> NOT </item>
-         </list>
-        <list name="types">
-            <item> bit </item>
-            <item> bit_vector </item>
-            <item> character </item>
-            <item> boolean </item>
-            <item> integer </item>
-            <item> real </item>
-            <item> time </item>
-            <item> string </item>
-            <item> severity_level </item>
-            <item> positive </item>
-            <item> natural </item>
-            <item> signed </item>
-            <item> unsigned </item>
-            <item> line </item>
-            <item> text </item>
-            <item> std_logic </item>
-            <item> std_logic_vector </item>
-            <item> std_ulogic </item>
-            <item> std_ulogic_vector </item>
-            <item> qsim_state </item>
-            <item> qsim_state_vector </item>
-            <item> qsim_12state </item>
-            <item> qsim_12state_vector </item>
-            <item> qsim_strength </item>
-            <item> mux_bit </item>
-            <item> mux_vector </item>
-            <item> reg_bit </item>
-            <item> reg_vector </item>
-            <item> wor_bit </item>
-            <item> wor_vector </item>
-            <item> BIT </item>
-            <item> BIT_VECTOR </item>
-            <item> CHARACTER </item>
-            <item> BOOLEAN </item>
-            <item> INTEGER </item>
-            <item> REAL </item>
-            <item> TIME </item>
-            <item> STRING </item>
-            <item> SEVERITY_LEVEL </item>
-            <item> POSITIVE </item>
-            <item> NATURAL </item>
-            <item> SIGNED </item>
-            <item> UNSIGNED </item>
-            <item> LINE </item>
-            <item> TEXT </item>
-            <item> STD_LOGIC </item>
-            <item> STD_LOGIC_VECTOR </item>
-            <item> STD_ULOGIC </item>
-            <item> STD_ULOGIC_VECTOR </item>
-            <item> QSIM_STATE </item>
-            <item> QSIM_STATE_VECTOR </item>
-            <item> QSIM_12STATE </item>
-            <item> QSIM_12STATE_VECTOR </item>
-            <item> QSIM_STRENGTH </item>
-            <item> MUX_BIT </item>
-            <item> MUX_VECTOR </item>
-            <item> REG_BIT </item>
-            <item> REG_VECTOR </item>
-            <item> WOR_BIT </item>
-            <item> WOR_VECTOR </item>
-        </list>
-        <contexts>
-            <context name="normal" attribute="Normal Text" lineEndContext="#stay">
-                <keyword attribute="Keyword" context="#stay"  String="keywords"/>
-                <keyword attribute="Data Type" context="#stay"  String="types"/>
-                <Detect2Chars attribute="Comment" context="comment" char="-" char1="-" />
-                <Int attribute="Integer" context="#stay" />
-                <HlCChar attribute="Bit" context="#stay" />
-                <DetectChar attribute="Vector" context="string" char="&quot;" />
-                <AnyChar attribute="Operator" context="#stay" String="[&amp;&gt;&lt;=:+\-*\/|]().,;" />
-                <DetectChar attribute="Attribute" context="attribute" char="'" />
-             </context>
-            <context name="comment" attribute="Comment" lineEndContext="#pop" />
-            <context name="string" attribute="Vector" lineEndContext="#stay" >
-                <DetectChar attribute="Vector" context="#pop" char="&quot;" />
-            </context>
-            <context name="attribute" attribute="Attribute" lineEndContext="#pop">
-                <DetectChar attribute="Attribute" context="quot in att" char="&quot;" />
-                <DetectChar attribute="Normal Text" context="#pop" char=" " />
-                <AnyChar attribute="Attribute" context="#pop" String=")=&lt;&gt;" />
-            </context>
-            <context name="quot in att" attribute="Attribute" lineEndContext="#stay">
-                <DetectChar attribute="Attribute" context="#pop" char="&quot;" />
-            </context>
-        </contexts>
-        <itemDatas>
-            <itemData name="Normal Text" defStyleNum="dsNormal" />
-            <itemData name="Keyword" defStyleNum="dsKeyword" />
-            <itemData name="Data Type" defStyleNum="dsDataType" />
-            <itemData name="Comment" defStyleNum="dsComment" />
-            <itemData name="Integer" defStyleNum="dsDecVal" />
-            <itemData name="Bit" defStyleNum="dsChar" />
-            <itemData name="Vector" defStyleNum="dsString" />
-            <itemData name="Operator" defStyleNum="dsOthers" />
-            <itemData name="Attribute" defStyleNum="dsBaseN" />
-        </itemDatas>
-    </highlighting>
+<!DOCTYPE language SYSTEM "language.dtd"
+[
+  <!ENTITY funcname "[A-Za-z_:][A-Za-z0-9_:#&#37;@-]*">
+  <!ENTITY varname  "[A-Za-z_][A-Za-z0-9_]*">
+  <!ENTITY bos      "(|[^&quot;-]*)\b">			<!-- bol or space following -->
+<!--  <!ENTITY bos      "^(|.*\s)">-->			<!-- bol or space following -->
+  <!ENTITY eos      "\b">		<!-- eol or space following -->
+<!--  <!ENTITY eos      "(?=($|\s))">-->		<!-- eol or space following -->
+  <!ENTITY noword   "(?![\w$+-])">		<!-- no word, $, + or - following -->
+  <!ENTITY label     "((&varname;)\s*:\s*)?">
+  
+]>
+<language name="VHDL" version="1.08" kateversion="2.3" section="Hardware" extensions="*.vhdl;*.vhd" mimetype="text/x-vhdl" author="Rocky Scaletta (rocky@purdue.edu), Stefan Endrullis (stefan@endrullis.de), Jan Michel (jan@mueschelsoft.de)">
+  <highlighting>
+    <list name="keywordsToplevel">
+      <item> file </item>
+      <item> package </item>
+      <item> library </item>
+      <item> use </item>
+<!--
+      <item> entity </item>
+      <item> architecture </item>
+      <item> of </item>
+      <item> configuration </item>
+-->
+    </list>
+    <list name="keywords">
+      <item> access </item>
+      <item> after </item>
+      <item> alias </item>
+      <item> all </item>
+      <item> assert </item>
+      <item> begin </item>
+      <item> block </item>
+      <item> body </item>
+      <item> bus </item>
+      <item> component </item>
+      <item> constant </item>
+      <item> disconnect </item>
+      <item> downto </item>
+      <item> end </item>
+      <item> exit </item>
+      <item> function </item>
+      <item> generate </item>
+      <item> generic </item>
+      <item> group </item>
+      <item> guarded </item>
+      <item> impure </item>
+      <item> inertial </item>
+      <item> is </item>
+      <item> label </item>
+      <item> linkage </item>
+      <item> literal </item>
+      <item> map </item>
+      <item> new </item>
+      <item> next </item>
+      <item> null </item>
+      <item> on </item>
+      <item> open </item>
+      <item> others </item>
+      <item> port </item>
+      <item> postponed </item>
+      <item> procedure </item>
+      <item> process </item>
+      <item> pure </item>
+      <item> range </item>
+      <item> record </item>
+      <item> register </item>
+      <item> reject </item>
+      <item> report </item>
+      <item> return </item>
+      <item> select </item>
+      <item> severity </item>
+      <item> signal </item>
+      <item> shared </item>
+      <item> subtype </item>
+      <item> then </item>
+      <item> to </item>
+      <item> transport </item>
+      <item> type </item>
+      <item> unaffected </item>
+      <item> units </item>
+      <item> until </item>
+      <item> variable </item>
+      <item> wait </item>
+      <item> when </item>
+      <item> with </item>
+      <item> note </item>
+      <item> warning </item>
+      <item> error </item>
+      <item> failure </item>
+      <item> in </item>
+      <item> inout </item>
+      <item> out </item>
+      <item> buffer </item>
+      <item> and </item>
+      <item> or </item>
+      <item> xor </item>
+      <item> not </item>
+    </list>
+    
+    <list name="if">
+      <item> else </item>
+      <item> elsif </item>
+    </list>
+    
+    <list name="forOrWhile">
+      <item> loop </item>
+    </list>
+      
+    <list name="directions">
+      <item> in </item>
+      <item> inout </item>
+      <item> out </item>
+      <item> buffer </item>
+    </list>
+    
+    <list name="signals">
+      <item> signal </item>
+      <item> variable </item>
+      <item> constant </item>
+      <item> type </item>      
+    </list>
+ <!--   <list name="logics">
+      <item> and </item>
+      <item> or </item>
+      <item> xor </item>
+      <item> not </item>
+    </list>
+    
+    <list name="rangeDirection">
+      <item> to </item>
+      <item> downto </item>
+    </list>-->
+    
+    <list name="types">
+      <item> bit </item>
+      <item> bit_vector </item>
+      <item> character </item>
+      <item> boolean </item>
+      <item> integer </item>
+      <item> real </item>
+      <item> time </item>
+      <item> string </item>
+      <item> severity_level </item>
+      <item> positive </item>
+      <item> natural </item>
+      <item> signed </item>
+      <item> unsigned </item>
+      <item> line </item>
+      <item> text </item>
+      <item> std_logic </item>
+      <item> std_logic_vector </item>
+      <item> std_ulogic </item>
+      <item> std_ulogic_vector </item>
+      <item> qsim_state </item>
+      <item> qsim_state_vector </item>
+      <item> qsim_12state </item>
+      <item> qsim_12state_vector </item>
+      <item> qsim_strength </item>
+      <item> mux_bit </item>
+      <item> mux_vector </item>
+      <item> reg_bit </item>
+      <item> reg_vector </item>
+      <item> wor_bit </item>
+      <item> wor_vector </item>
+    </list>
+    <contexts>
+      <!-- start / global environment -->
+      <context name="start" attribute="Normal Text" lineEndContext="#stay">
+        <RegExpr attribute="Normal Text" context="entity" String="&bos;(entity\s*(&varname;)\s*is)&eos;" beginRegion="EntityRegion1" lookAhead="true" insensitive="true" />
+        <RegExpr attribute="Normal Text" context="architecture" String="&bos;(architecture\s*(&varname;)\s*of\s*&varname;\s*is)&eos;" beginRegion="ArchitectureRegion1" lookAhead="true" insensitive="true" />
+        <Detect2Chars attribute="Comment" context="comment" char="-" char1="-" />
+        <keyword attribute="Keyword" context="#stay"  String="keywordsToplevel"/>
+      </context>
+      
+      <context name="preDetection" attribute="Normal Text" lineEndContext="#stay">
+        <Detect2Chars attribute="Comment" context="comment" char="-" char1="-" />
+        <DetectChar attribute="Vector" context="string" char="&quot;" />
+        <AnyChar attribute="Operator" context="#stay" String="[&amp;&gt;&lt;=:+\-*\/|]().,;" />
+        <DetectChar attribute="Attribute" context="attribute" char="'" />
+      </context>
+      
+      <!-- general keywords detection -->
+      <context name="generalDetection" attribute="Normal Text" lineEndContext="#stay">
+        <keyword attribute="Data Type" context="#stay"  String="types"/>
+        <keyword attribute="Signal" context="#stay"  String="signals"/>
+        <keyword attribute="Keyword" context="#stay"  String="keywords"/>
+        <Int attribute="Integer" context="#stay" />
+        <HlCChar attribute="Bit" context="#stay" />
+      </context>
+      
+
+      
+      <!-- entity environment -->
+      <context name="entity" attribute="Normal Text" lineEndContext="#stay" dynamic="true">
+        <StringDetect attribute="Redirection" context="#stay" String="%2" dynamic="true" />
+        <IncludeRules context="preDetection" />
+        <RegExpr attribute="Redirection" context="#pop" String="^(|\s.*)end(\s*entity)?\s*(%3)?\s*;" dynamic="true" endRegion="EntityRegion1" insensitive="true" />
+        <!--<RegExpr attribute="Alert" context="generic" String="generic"/>-->
+        <IncludeRules context="generalDetection" />
+      </context>
+<!--      <context name="generic" attribute="Normal Text" lineEndContext="#stay">
+        <DetectChar attribute="Operator" context="range" char="("/>
+        <Detect2Chars attribute="Alert" context="#pop" char=")" char1=";"/>
+      </context>
+      <context name="range" attribute="Normal Text" lineEndContext="#stay">
+        <keyword attribute="Keyword" context="#stay"  String="rangeDirection"/>
+        <Int attribute="Integer" context="#stay" />
+        <HlCChar attribute="Bit" context="#stay" />
+        <DetectChar attribute="Vector" context="string" char="&quot;" />
+        <DetectChar attribute="Operator" context="#pop" char=")"/>
+      </context>-->
+      
+      <!-- architecture environment -->
+      <context name="architecture" attribute="Normal Text" lineEndContext="#stay" dynamic="true">
+        <StringDetect attribute="Redirection" context="#stay" String="%2" dynamic="true" />
+        <IncludeRules context="preDetection" />
+        <StringDetect attribute="Redirection" context="#stay" String="begin" insensitive="true" />
+        <RegExpr attribute="Redirection" context="#pop" String="&bos;end(\s+architecture)?(\s+%3)?\s*;" dynamic="true" endRegion="ArchitectureRegion1"  insensitive="true" />
+        <RegExpr attribute="Normal Text" context="component" String="&bos;(component\s+(&varname;)(\s+is)?)&eos;" beginRegion="ComponentRegion1" lookAhead="true"  insensitive="true" />
+        <RegExpr attribute="Normal Text" context="process1" String="^(|\s+)(&label;process)&eos;" beginRegion="ProcessRegion1" lookAhead="true"  insensitive="true" />
+        <RegExpr attribute="Normal Text" context="generate1" String="^(|\s+)((&varname;)\s*:\s*((for\s+.+\s+in\s+.+)|(if\s+.+))\s+generate)&eos;" beginRegion="GenerateRegion1" lookAhead="true" insensitive="true" />
+        <RegExpr attribute="Normal Text" context="instance" String="^(|\s+)((&varname;)\s*:\s*(&varname;))&eos;" beginRegion="InstanceRegion1" lookAhead="true"  insensitive="true" />
+        <IncludeRules context="generalDetection" />
+      </context>
+<!--      <context name="architectureBeforeBegin" attribute="Normal Text" lineEndContext="#stay" dynamic="true">
+        <StringDetect attribute="Redirection" context="#stay" String="%1" dynamic="true" />
+        <RegExpr attribute="Redirection" context="#pop" String="end\s*%2\s*;" dynamic="true" endRegion="ArchitectureRegion1" />
+        <StringDetect attribute="Redirection" context="architectureAfterBegin" String="begin" />
+        <RegExpr attribute="Redirection" context="#pop#pop" String="end\s*%2\s*;" dynamic="true" endRegion="ArchitectureRegion1" />
+        <IncludeRules context="normal" />
+      </context>
+      <context name="architectureAfterBegin" attribute="Normal Text" lineEndContext="#stay" dynamic="true">
+        <StringDetect attribute="Redirection" context="#stay" String="%1" dynamic="true" />
+        <IncludeRules context="normal" />
+      </context>-->
+      
+      <!-- component environment -->
+      <context name="component" attribute="Normal Text" lineEndContext="#stay" dynamic="true">
+        <StringDetect attribute="Redirection" context="" String="%2" dynamic="true" />
+        <IncludeRules context="preDetection" />
+        <RegExpr attribute="Redirection" context="#pop" String="&bos;end\s+component(\s+%3)?\s*;" dynamic="true" endRegion="ComponentRegion1" insensitive="true" />
+        <IncludeRules context="generalDetection" />
+      </context>
+
+      <!-- generate statement -->
+      <context name="generate1" attribute="Normal Text" lineEndContext="#stay" dynamic="true">
+        <StringDetect attribute="Process" context="generate2" String="%2" dynamic="true" />
+      </context>
+      <context name="generate2" attribute="Normal Text" lineEndContext="#stay" dynamic="true">
+        <IncludeRules context="architecture" />
+        <RegExpr attribute="Process" context="#pop#pop" String="^(|\s.*)end\s+generate(?:\s+%3)?\s*;" dynamic="true" endRegion="GenerateRegion1" insensitive="true" />
+      </context>
+
+      <context name="instance" attribute="Normal Text" lineEndContext="#stay" dynamic="true">
+        <StringDetect attribute="Redirection" context="#stay" String="%2" dynamic="true" />
+        <Detect2Chars attribute="Comment" context="comment" char="-" char1="-" />
+        <DetectChar attribute="Vector" context="string" char="&quot;" />
+        <Detect2Chars attribute="Normal Text" context="#pop" char=")" char1=";" endRegion="InstanceRegion1" />
+        <IncludeRules context="generalDetection" />
+        <AnyChar attribute="Operator" context="#stay" String="[&amp;&gt;&lt;=:+\-*\/|]().,;" />
+        <DetectChar attribute="Attribute" context="attribute" char="'" />
+      </context>
+      
+      <!-- process environment -->
+      <context name="process1" attribute="Normal Text" lineEndContext="#stay" dynamic="true">
+        <StringDetect attribute="Process" context="process2" String="%2" dynamic="true" />
+        <RegExpr attribute="Process" context="#pop" String="^(|\s.*)end\s+process(\s+%4)?\s*;" endRegion="ProcessRegion1" insensitive="true" dynamic="true" />
+      </context>
+      <context name="process2" attribute="Normal Text" lineEndContext="#stay" dynamic="true">
+        <RegExpr attribute="Process" context="#pop" String="^(|\s.*)end\s+process" insensitive="true" lookAhead="true" />
+        <StringDetect attribute="Process" context="#stay" String="begin" insensitive="true" />
+        <IncludeRules context="processContext" />
+      </context>
+
+      <context name="processContext" attribute="Normal Text" lineEndContext="#stay">
+        <IncludeRules context="preDetection" />
+        <RegExpr attribute="Control" context="case1" String="&bos;&label;(case)&eos;" beginRegion="CaseRegion1" insensitive="true" />
+        <RegExpr attribute="Control" context="if" String="&bos;&label;(if)&eos;" beginRegion="IfRegion1" insensitive="true" />
+        <RegExpr attribute="Control" context="forOrWhile" String="&bos;&label;((for|while)\s+.+\s+)?loop&eos;" beginRegion="ForOrWhileRegion1" insensitive="true" />
+        <IncludeRules context="generalDetection" />
+      </context>
+      <context name="case1" attribute="Normal Text" lineEndContext="#stay">
+        <StringDetect attribute="Keyword" context="case2" String="is" insensitive="true" />
+      </context>
+      <context name="case2" attribute="Normal Text" lineEndContext="#stay">
+        <RegExpr attribute="Control" context="#pop#pop" String="&bos;end\s+case(\s+&varname;)?\s*;" endRegion="CaseRegion1" insensitive="true" />
+        <RegExpr attribute="Control" context="caseWhen" String="&bos;when&eos;" beginRegion="CaseWhenRegion1" insensitive="true" />
+        <IncludeRules context="processContext" />
+      </context>
+      <context name="caseWhen" attribute="Normal Text" lineEndContext="#stay">
+        <RegExpr attribute="Control" context="#pop" String="&bos;when&eos;" endRegion="CaseWhenRegion1" lookAhead="true" insensitive="true" />
+        <RegExpr attribute="Control" context="#pop" String="&bos;end\s+case(\s+&varname;)?\s*;" endRegion="CaseWhenRegion1" lookAhead="true" insensitive="true" />
+        <IncludeRules context="process2" />
+      </context>
+      <context name="if" attribute="Normal Text" lineEndContext="#stay">
+        <RegExpr attribute="Control" context="#pop" String="&bos;end\s+if(\s+&varname;)?\s*;" endRegion="IfRegion1" insensitive="true" />
+        <keyword attribute="Control" context="#stay"  String="if"/>
+        <IncludeRules context="processContext" />
+      </context>
+      <context name="forOrWhile" attribute="Normal Text" lineEndContext="#stay">
+        <RegExpr attribute="Control" context="#pop" String="&bos;end\s+loop(\s+&varname;)?\s*;" endRegion="ForOrWhileRegion1" insensitive="true" />
+        <keyword attribute="Control" context="#stay"  String="forOrWhile"/>
+        <IncludeRules context="processContext" />
+      </context>
+      
+      <!-- other environments -->
+      <context name="comment" attribute="Comment" lineEndContext="#pop" />
+      <context name="string" attribute="Vector" lineEndContext="#stay" >
+        <DetectChar attribute="Vector" context="#pop" char="&quot;" />
+      </context>
+      <context name="attribute" attribute="Attribute" lineEndContext="#pop">
+        <DetectChar attribute="Attribute" context="quot in att" char="&quot;" />
+        <DetectChar attribute="Normal Text" context="#pop" char=" " />
+        <AnyChar attribute="Attribute" context="#pop" String=")=&lt;&gt;" />
+      </context>
+      <context name="quot in att" attribute="Attribute" lineEndContext="#stay">
+        <DetectChar attribute="Attribute" context="#pop" char="&quot;" />
+      </context>
+    </contexts>
+    <itemDatas>
+      <itemData name="Normal Text" defStyleNum="dsNormal" />
+      <itemData name="Keyword" defStyleNum="dsKeyword" />
+      <itemData name="Data Type" defStyleNum="dsDataType" />
+      <itemData name="Comment" defStyleNum="dsComment" />
+      <itemData name="Integer" defStyleNum="dsDecVal" />
+      <itemData name="Bit" defStyleNum="dsChar" />
+      <itemData name="Vector" defStyleNum="dsString" />
+      <itemData name="Operator" defStyleNum="dsOthers" />
+      <itemData name="Attribute" defStyleNum="dsBaseN" />
+      <itemData name="Region Marker" defStyleNum="dsRegionMarker" />
+      <itemData name="Signal" defStyleNum="dsOthers"/>
+      <itemData name="Redirection" defStyleNum="dsKeyword" color="#238" />
+      <itemData name="Process" defStyleNum="dsKeyword" color="#09A" />
+      <itemData name="Control" defStyleNum="dsKeyword" color="#008" />
+    </itemDatas>
+  </highlighting>
   <general>
     <comments>
       <comment name="singleLine" start="--" />
     </comments>
-    <keywords casesensitive="1" />
+    <keywords casesensitive="0" />
   </general>
-</language>
-
+</language>
\ No newline at end of file