blob: 36a778cfc9e24adea098acfbba6e5770e254318a (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
|
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE language SYSTEM "language.dtd">
<language name="Verilog" version="2" kateversion="2.4" section="Hardware" extensions="*.v;*.V;*.vl" mimetype="text/x-verilog-src" author="Yevgen Voronenko (ysv22@drexel.edu), Ryan Dalzell (ryan@tullyroan.com)" license="">
<highlighting>
<list name="keywords">
<item> macromodule </item>
<item> table </item>
<item> endtable </item>
<item> specify </item>
<item> specparam </item>
<item> endspecify </item>
<item> defparam </item>
<item> default </item>
<item> if </item>
<item> ifnone </item>
<item> else </item>
<item> forever </item>
<item> while </item>
<item> for </item>
<item> wait </item>
<item> repeat </item>
<item> disable </item>
<item> assign </item>
<item> deassign </item>
<item> force </item>
<item> release </item>
<item> always </item>
<item> initial </item>
<item> edge </item>
<item> posedge </item>
<item> negedge </item>
<!-- verilog-2001 keywords -->
<item> config </item>
<item> endconfig </item>
<item> library </item>
<item> design </item>
<item> liblist </item>
<item> cell </item>
<item> use </item>
<item> instance </item>
</list>
<list name="beginwords">
<item> begin </item>
<item> fork </item>
<item> module </item>
<item> case </item>
<item> casex </item>
<item> casez </item>
<item> task </item>
<item> function </item>
<item> generate </item>
</list>
<list name="endwords">
<item> end </item>
<item> join </item>
<item> endmodule </item>
<item> endcase </item>
<item> endtask </item>
<item> endfunction </item>
<item> endgenerate </item>
</list>
<list name="strength">
<!-- drive strength supply0/supply1 omitted, its in types.. -->
<item> strong0 </item>
<item> strong1 </item>
<item> pull0 </item>
<item> pull1 </item>
<item> weak0 </item>
<item> weak1 </item>
<item> highz0 </item>
<item> highz1 </item>
<!-- charge strength -->
<item> small </item>
<item> medium </item>
<item> large </item>
</list>
<list name="gates">
<item> pullup </item>
<item> pulldown </item>
<item> cmos </item>
<item> rcmos </item>
<item> nmos </item>
<item> pmos </item>
<item> rnmos </item>
<item> rpmos </item>
<item> and </item>
<item> nand </item>
<item> or </item>
<item> nor </item>
<item> xor </item>
<item> xnor </item>
<item> not </item>
<item> buf </item>
<item> tran </item>
<item> rtran </item>
<item> tranif0 </item>
<item> tranif1 </item>
<item> rtranif0 </item>
<item> rtranif1 </item>
<item> bufif0 </item>
<item> bufif1 </item>
<item> notif0 </item>
<item> notif1 </item>
</list>
<list name="types">
<!-- port direction -->
<item> input </item>
<item> output </item>
<item> inout </item>
<!-- net type -->
<item> wire </item>
<item> tri </item>
<item> tri0 </item>
<item> tri1 </item>
<item> wand </item>
<item> wor </item>
<item> triand </item>
<item> trior </item>
<item> supply0 </item>
<item> supply1 </item>
<!-- reg/variable -->
<item> reg </item>
<item> integer </item>
<item> real </item>
<item> realtime </item>
<item> time </item>
<!-- modifier -->
<item> vectored </item>
<item> scalared </item>
<item> trireg </item>
<!-- other -->
<item> parameter </item>
<item> event </item>
<!-- verilog-2001 types -->
<item> signed </item>
<item> automatic </item>
<item> genvar </item>
<item> localparam </item>
</list>
<contexts>
<context attribute="Normal Text" lineEndContext="#stay" name="Normal">
<DetectSpaces />
<RegExpr attribute="Keyword" context="Block name" String="begin\ *:" beginRegion="Block"/>
<RegExpr attribute="Keyword" context="Block name" String="fork\ *:" beginRegion="Block"/>
<keyword attribute="Keyword" String="beginwords" context="#stay" beginRegion="Block"/>
<keyword attribute="Keyword" String="endwords" context="#stay" endRegion="Block"/>
<keyword attribute="Keyword" context="#stay" String="keywords" />
<keyword attribute="Data Type" context="#stay" String="types" />
<keyword attribute="Drive/charge strength" context="#stay" String="strength" />
<keyword attribute="Gate instantiation" context="#stay" String="gates" />
<RegExpr attribute="Decimal" context="#stay" String="[\d_]*'d[\d_]+"/>
<RegExpr attribute="Octal" context="#stay" String="[\d_]*'o[0-7xXzZ_]+"/>
<RegExpr attribute="Hex" context="#stay" String="[\d_]*'h[\da-fA-FxXzZ_]+"/>
<RegExpr attribute="Binary" context="#stay" String="[\d_]*'b[01_zZxX]+"/>
<Float attribute="Float" context="#stay"/>
<Int attribute="Integer" context="#stay" />
<RegExpr attribute="Case label" context="#stay" String="[a-zA-Z0-9_, \t]+\s*:" firstNonSpace="true"/>
<!--<RegExpr attribute="Port map" context="Port" String="\.[a-zA-Z0-9_]+"/>-->
<DetectChar attribute="String" context="String" char="""/>
<Detect2Chars attribute="Comment" context="Commentar 1" char="/" char1="/"/>
<Detect2Chars attribute="Comment" context="Commentar 2" char="/" char1="*" beginRegion="Comment"/>
<AnyChar attribute="Symbol" context="#stay" String="!%&()+,-<=+/:;>?[]^{|}~@"/>
<DetectChar attribute="Preprocessor" context="Preprocessor" char="`" column="0"/>
<RegExpr attribute="Preprocessor" context="#stay" String="\`[a-zA-Z_]+\w*" />
<RegExpr attribute="System Task" context="#stay" String="\$[a-zA-Z_]+\w*" />
<RegExpr attribute="Delay" context="#stay" String="#[\d_]+" />
</context>
<context attribute="String" lineEndContext="#pop" name="String">
<LineContinue attribute="String" context="Some Context"/>
<HlCStringChar attribute="String Char" context="#stay"/>
<DetectChar attribute="String" context="#pop" char="""/>
</context>
<context attribute="Comment" lineEndContext="#pop" name="Commentar 1">
<IncludeRules context="##Alerts" />
</context>
<context attribute="Comment" lineEndContext="#stay" name="Commentar 2">
<IncludeRules context="##Alerts" />
<Detect2Chars attribute="Comment" context="#pop" char="*" char1="/" endRegion="Comment"/>
</context>
<context attribute="Preprocessor" lineEndContext="#pop" name="Preprocessor">
<LineContinue attribute="Preprocessor" context="Some Context"/>
<RangeDetect attribute="Prep. Lib" context="#stay" char=""" char1="""/>
<RangeDetect attribute="Prep. Lib" context="#stay" char="<" char1=">"/>
<Detect2Chars attribute="Comment" context="Commentar 1" char="/" char1="/"/>
<Detect2Chars attribute="Comment" context="Commentar/Preprocessor" char="/" char1="*"/>
</context>
<context attribute="Comment" lineEndContext="#stay" name="Commentar/Preprocessor">
<Detect2Chars attribute="Comment" context="#pop" char="*" char1="/" />
</context>
<context attribute="Normal Text" lineEndContext="#pop" name="Some Context"/>
<context attribute="Comment" lineEndContext="#stay" name="Some Context2">
<IncludeRules context="##Alerts" />
<StringDetect attribute="Comment" context="#pop" String="#endif" firstNonSpace="true"/>
</context>
<context attribute="Block name" lineEndContext="#pop" name="Block name">
<DetectIdentifier attribute="Data Type" context="#pop"/>
</context>
<context attribute="Normal Text" lineEndContext="#stay" name="Port">
<DetectIdentifier attribute="Normal Text" context="#pop"/>
</context>
</contexts>
<itemDatas>
<itemData name="Normal Text" defStyleNum="dsNormal"/>
<itemData name="Keyword" defStyleNum="dsKeyword"/>
<itemData name="Data Type" defStyleNum="dsDataType"/>
<itemData name="Decimal" defStyleNum="dsBaseN"/>
<itemData name="Octal" defStyleNum="dsBaseN"/>
<itemData name="Hex" defStyleNum="dsBaseN"/>
<itemData name="Binary" defStyleNum="dsBaseN"/>
<itemData name="Float" defStyleNum="dsFloat"/>
<itemData name="String" defStyleNum="dsString"/>
<itemData name="String Char" defStyleNum="dsChar"/>
<itemData name="Comment" defStyleNum="dsComment"/>
<itemData name="Alert" defStyleNum="dsAlert" />
<itemData name="Symbol" defStyleNum="dsNormal"/>
<itemData name="Preprocessor" defStyleNum="dsOthers"/>
<itemData name="Prep. Lib" defStyleNum="dsFloat"/>
<itemData name="System Task" defStyleNum="dsDataType"/>
<itemData name="Integer" defStyleNum="dsDecVal"/>
<itemData name="Delay" defStyleNum="dsBaseN"/>
<itemData name="Block name" defStyleNum="dsDataType"/>
<itemData name="Drive/charge strength" defStyleNum="dsBaseN"/>
<itemData name="Gate instantiation" defStyleNum="dsDataType"/>
<itemData name="Port map" defStyleNum="dsDataType"/>
<itemData name="Case label" defStyleNum="dsDecVal"/>
</itemDatas>
</highlighting>
<general>
<comments>
<comment name="singleLine" start="//" />
<comment name="multiLine" start="/*" end="*/" region="Comment"/>
</comments>
<keywords casesensitive="1" />
</general>
</language>
|
