TQt4 port piklab

This enables compilation under both Qt3 and Qt4


git-svn-id: svn://anonsvn.kde.org/home/kde/branches/trinity/applications/piklab@1238822 283d02a7-25f6-0310-bc7c-ecb5cbfe19da

1 files changed, 61 insertions, 61 deletions

diff --git a/src/devices/pic/xml_data/18F442.xml b/src/devices/pic/xml_data/18F442.xml
index 61f6a63..1a864f5 100644
--- a/src/devices/pic/xml_data/18F442.xml
+++ b/src/devices/pic/xml_data/18F442.xml
@@ -34,17 +34,17 @@
 
 <!--* Memory ***************************************************************-->
   <memory name="code"      start="0x000000" end="0x003FFF" word_write_align="4" word_erase_align="32" />
-  <memory name="user_ids"     start="0x200000" end="0x200007" rmask="0x0F"              />
+  <memory name="user_ids"     start="0x200000" end="0x200007" rtqmask="0x0F"              />
   <memory name="device_id"    start="0x3FFFFE" end="0x3FFFFF" />
   <memory name="config"       start="0x300000" end="0x30000D" />
   <memory name="eeprom"       start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" />
   <memory name="debug_vector" start="0x200028" end="0x200037" />
 
 <!--* Configuration bits ***************************************************-->
-  <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" />
+  <config offset="0x0" name="CONFIG1L" wtqmask="0xFF" bvalue="0x00" />
 
-  <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x27" >
-    <mask name="FOSC"   value="0x07" >
+  <config offset="0x1" name="CONFIG1H" wtqmask="0xFF" bvalue="0x27" >
+    <tqmask name="FOSC"   value="0x07" >
       <value value="0x00" name="LP"           cname="_LP_OSC"    sdcc_cname="_OSC_LP" />
       <value value="0x01" name="XT"           cname="_XT_OSC"    sdcc_cname="_OSC_XT" />
       <value value="0x02" name="HS"           cname="_HS_OSC"    sdcc_cname="_OSC_HS" />
@@ -53,36 +53,36 @@
       <value value="0x05" name="EC_IO"        cname="_ECIO_OSC"  sdcc_cname="_OSC_EC_OSC2_RA6" />
       <value value="0x06" name="H4"           cname="_HSPLL_OSC" sdcc_cname="_OSC_HS_PLL" />
       <value value="0x07" name="EXTRC_IO"     cname="_RCIO_OSC"  sdcc_cname="_OSC_RC_OSC2" />
-    </mask>
-    <mask name="OSCSEN" value="0x20" >
+    </tqmask>
+    <tqmask name="OSCSEN" value="0x20" >
       <value value="0x00" name="On"  cname="_OSCS_ON"  />
       <value value="0x20" name="Off" cname="_OSCS_OFF" />
-    </mask>
+    </tqmask>
   </config>
 
-  <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x0F" >
-    <mask name="PWRTE" value="0x01" >
+  <config offset="0x2" name="CONFIG2L" wtqmask="0xFF" bvalue="0x0F" >
+    <tqmask name="PWRTE" value="0x01" >
       <value value="0x00" name="On"  cname="_PWRT_ON"  sdcc_cname="_PUT_ON" />
       <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" />
-    </mask>
-    <mask name="BODEN" value="0x02" >
+    </tqmask>
+    <tqmask name="BODEN" value="0x02" >
       <value value="0x00" name="Off" cname="_BOR_OFF" sdcc_cname="_BODEN_OFF" />
       <value value="0x02" name="On"  cname="_BOR_ON"  sdcc_cname="_BODEN_ON" />
-    </mask>
-    <mask name="BORV"  value="0x0C" >
+    </tqmask>
+    <tqmask name="BORV"  value="0x0C" >
       <value value="0x00" name="4.5" cname="_BORV_45" sdcc_cname="_BODENV_4_5V" />
       <value value="0x04" name="4.2" cname="_BORV_42" sdcc_cname="_BODENV_4_2V" />
       <value value="0x08" name="2.7" cname="_BORV_27" sdcc_cname="_BODENV_2_7V" />
       <value value="0x0C" name="2.0" cname="_BORV_20" sdcc_cname="_BODENV_2_0V" />
-    </mask>
+    </tqmask>
   </config>
 
-  <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x0F" >
-    <mask name="WDT"   value="0x01" >
+  <config offset="0x3" name="CONFIG2H" wtqmask="0xFF" bvalue="0x0F" >
+    <tqmask name="WDT"   value="0x01" >
       <value value="0x00" name="Off" cname="_WDT_OFF" />
       <value value="0x01" name="On"  cname="_WDT_ON"  />
-    </mask>
-    <mask name="WDTPS" value="0x0E" >
+    </tqmask>
+    <tqmask name="WDTPS" value="0x0E" >
       <value value="0x00" name="1:1"   cname="_WDTPS_1"   sdcc_cname="_WDTPS_1_1" />
       <value value="0x02" name="1:2"   cname="_WDTPS_2"   sdcc_cname="_WDTPS_1_2" />
       <value value="0x04" name="1:4"   cname="_WDTPS_4"   sdcc_cname="_WDTPS_1_4" />
@@ -91,99 +91,99 @@
       <value value="0x0A" name="1:32"  cname="_WDTPS_32"  sdcc_cname="_WDTPS_1_32" />
       <value value="0x0C" name="1:64"  cname="_WDTPS_64"  sdcc_cname="_WDTPS_1_64" />
       <value value="0x0E" name="1:128" cname="_WDTPS_128" sdcc_cname="_WDTPS_1_128" />
-    </mask>
+    </tqmask>
   </config>
 
-  <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" />
+  <config offset="0x4" name="CONFIG3L" wtqmask="0xFF" bvalue="0x00" />
 
-  <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x01" >
-    <mask name="CCP2MX" value="0x01" >
+  <config offset="0x5" name="CONFIG3H" wtqmask="0xFF" bvalue="0x01" >
+    <tqmask name="CCP2MX" value="0x01" >
       <value value="0x00" name="RB3" cname="_CCP2MX_OFF" sdcc_cname="_CCP2MUX_RB3" />
       <value value="0x01" name="RC1" cname="_CCP2MX_ON"  sdcc_cname="_CCP2MUX_RC1"/>
-    </mask>
+    </tqmask>
   </config>
 
-  <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" >
-    <mask name="STVREN" value="0x01" >
+  <config offset="0x6" name="CONFIG4L" wtqmask="0xFF" bvalue="0x85" >
+    <tqmask name="STVREN" value="0x01" >
       <value value="0x00" name="Off" cname="_STVR_OFF" />
       <value value="0x01" name="On"  cname="_STVR_ON"  />
-    </mask>
-    <mask name="LVP"    value="0x04" >
+    </tqmask>
+    <tqmask name="LVP"    value="0x04" >
       <value value="0x00" name="Off" cname="_LVP_OFF" />
       <value value="0x04" name="On"  cname="_LVP_ON"  />
-    </mask>
-    <mask name="DEBUG"  value="0x80" >
+    </tqmask>
+    <tqmask name="DEBUG"  value="0x80" >
       <value value="0x00" name="On"  cname="_DEBUG_ON"  sdcc_cname="_BACKBUG_ON" />
       <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" />
-    </mask>
+    </tqmask>
   </config>
 
-  <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" />
+  <config offset="0x7" name="CONFIG4H" wtqmask="0xFF" bvalue="0x00" />
 
-  <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x03" >
-    <mask name="CP_0" value="0x01" >
+  <config offset="0x8" name="CONFIG5L" wtqmask="0xFF" bvalue="0x03" >
+    <tqmask name="CP_0" value="0x01" >
       <value value="0x00" name="0200:1FFF" cname="_CP0_ON"  sdcc_cname="_CP_0_ON" />
       <value value="0x01" name="Off"       cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" />
-    </mask>
-    <mask name="CP_1" value="0x02" >
+    </tqmask>
+    <tqmask name="CP_1" value="0x02" >
       <value value="0x00" name="2000:3FFF" cname="_CP1_ON"  sdcc_cname="_CP_1_ON" />
       <value value="0x02" name="Off"       cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" />
-    </mask>
+    </tqmask>
   </config>
 
-  <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0xC0" >
-    <mask name="CPB" value="0x40" >
+  <config offset="0x9" name="CONFIG5H" wtqmask="0xFF" bvalue="0xC0" >
+    <tqmask name="CPB" value="0x40" >
       <value value="0x00" name="0000:01FF" cname="_CPB_ON"  />
       <value value="0x40" name="Off"       cname="_CPB_OFF" />
-    </mask>
-    <mask name="CPD" value="0x80" >
+    </tqmask>
+    <tqmask name="CPD" value="0x80" >
       <value value="0x00" name="All" cname="_CPD_ON"  />
       <value value="0x80" name="Off" cname="_CPD_OFF" />
-    </mask>
+    </tqmask>
   </config>
 
-  <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x03" >
-    <mask name="WRT_0" value="0x01" >
+  <config offset="0xA" name="CONFIG6L" wtqmask="0xFF" bvalue="0x03" >
+    <tqmask name="WRT_0" value="0x01" >
       <value value="0x00" name="0200:1FFF" cname="_WRT0_ON"  sdcc_cname="_WRT_0_ON" />
       <value value="0x01" name="Off"       cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" />
-    </mask>
-    <mask name="WRT_1" value="0x02" >
+    </tqmask>
+    <tqmask name="WRT_1" value="0x02" >
       <value value="0x00" name="2000:3FFF" cname="_WRT1_ON"  sdcc_cname="_WRT_1_ON" />
       <value value="0x02" name="Off"       cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" />
-    </mask>
+    </tqmask>
   </config>
 
-  <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0xE0" >
-    <mask name="WRTC" value="0x20" >
+  <config offset="0xB" name="CONFIG6H" wtqmask="0xFF" bvalue="0xE0" >
+    <tqmask name="WRTC" value="0x20" >
       <value value="0x00" name="All" cname="_WRTC_ON"  />
       <value value="0x20" name="Off" cname="_WRTC_OFF" />
-    </mask>
-    <mask name="WRTB" value="0x40" >
+    </tqmask>
+    <tqmask name="WRTB" value="0x40" >
       <value value="0x00" name="0000:01FF" cname="_WRTB_ON"  />
       <value value="0x40" name="Off"       cname="_WRTB_OFF" />
-    </mask>
-    <mask name="WRTD" value="0x80" >
+    </tqmask>
+    <tqmask name="WRTD" value="0x80" >
       <value value="0x00" name="All" cname="_WRTD_ON"  />
       <value value="0x80" name="Off" cname="_WRTD_OFF" />
-    </mask>
+    </tqmask>
   </config>
 
-  <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x03" >
-    <mask name="EBTR_0" value="0x01" >
+  <config offset="0xC" name="CONFIG7L" wtqmask="0xFF" bvalue="0x03" >
+    <tqmask name="EBTR_0" value="0x01" >
       <value value="0x00" name="0200:1FFF" cname="_EBTR0_ON"  sdcc_cname="_EBTR_0_ON" />
       <value value="0x01" name="Off"       cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" />
-    </mask>
-    <mask name="EBTR_1" value="0x02" >
+    </tqmask>
+    <tqmask name="EBTR_1" value="0x02" >
       <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON"  sdcc_cname="_EBTR_1_ON" />
       <value value="0x02" name="Off"       cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" />
-    </mask>
+    </tqmask>
   </config>
 
-  <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" >
-    <mask name="EBTRB" value="0x40" >
+  <config offset="0xD" name="CONFIG7H" wtqmask="0xFF" bvalue="0x40" >
+    <tqmask name="EBTRB" value="0x40" >
       <value value="0x00" name="0000:01FF" cname="_EBTRB_ON"  />
       <value value="0x40" name="Off"       cname="_EBTRB_OFF" />
-    </mask>
+    </tqmask>
   </config>
 
 <!--* Packages *************************************************************-->