diff options
Diffstat (limited to 'src/devices/pic/xml_data/18F4550.xml')
| -rw-r--r-- | src/devices/pic/xml_data/18F4550.xml | 178 |
1 files changed, 89 insertions, 89 deletions
diff --git a/src/devices/pic/xml_data/18F4550.xml b/src/devices/pic/xml_data/18F4550.xml index d988438..b0e26c8 100644 --- a/src/devices/pic/xml_data/18F4550.xml +++ b/src/devices/pic/xml_data/18F4550.xml @@ -26,15 +26,15 @@ <!--* Memory ***************************************************************--> <memory name="code" start="0x000000" end="0x007FFF" word_write_align="16" word_erase_align="32" /> - <memory name="user_ids" start="0x200000" end="0x200007" rtqmask="0x0F" /> + <memory name="user_ids" start="0x200000" end="0x200007" rmask="0x0F" /> <memory name="device_id" start="0x3FFFFE" end="0x3FFFFF" /> <memory name="config" start="0x300000" end="0x30000D" /> <memory name="eeprom" start="0x000000" end="0x0000FF" hexfile_offset="0xF00000" /> <memory name="debug_vector" start="0x200028" end="0x200037" /> <!--* Configuration bits ***************************************************--> - <config offset="0x0" name="CONFIG1L" wtqmask="0xFF" bvalue="0x00" > - <tqmask name="PLLDIV" value="0x07" > + <config offset="0x0" name="CONFIG1L" wmask="0xFF" bvalue="0x00" > + <mask name="PLLDIV" value="0x07" > <value value="0x00" name="1" cname="_PLLDIV_1" sdcc_cname="_PLLDIV_NO_DIVIDE__4MHZ_INPUT_" /> <value value="0x01" name="2" cname="_PLLDIV_2" sdcc_cname="_PLLDIV_DIVIDE_BY_2__8MHZ_INPUT_" /> <value value="0x02" name="3" cname="_PLLDIV_3" sdcc_cname="_PLLDIV_DIVIDE_BY_3__12MHZ_INPUT_" /> @@ -43,21 +43,21 @@ <value value="0x05" name="6" cname="_PLLDIV_6" sdcc_cname="_PLLDIV_DIVIDE_BY_6__24MHZ_INPUT_" /> <value value="0x06" name="10" cname="_PLLDIV_10" sdcc_cname="_PLLDIV_DIVIDE_BY_10__40MHZ_INPUT_" /> <value value="0x07" name="12" cname="_PLLDIV_12" sdcc_cname="_PLLDIV_DIVIDE_BY_12__48MHZ_INPUT_" /> - </tqmask> - <tqmask name="CPUDIV" value="0x18" > + </mask> + <mask name="CPUDIV" value="0x18" > <value value="0x00" name="1" cname="_CPUDIV_OSC1_PLL2" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___1__96MHZ_PLL_SRC___2_" /> <value value="0x08" name="2" cname="_CPUDIV_OSC2_PLL3" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___2__96MHZ_PLL_SRC___3_" /> <value value="0x10" name="3" cname="_CPUDIV_OSC3_PLL4" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___3__96MHZ_PLL_SRC___4_" /> <value value="0x18" name="4" cname="_CPUDIV_OSC4_PLL6" sdcc_cname="_CPUDIV__OSC1_OSC2_SRC___4__96MHZ_PLL_SRC___6_" /> - </tqmask> - <tqmask name="USBDIV" value="0x20" > + </mask> + <mask name="USBDIV" value="0x20" > <value value="0x00" name="1" cname="_USBDIV_1" sdcc_cname="_USBPLL_CLOCK_SRC_FROM_OSC1_OSC2" /> <value value="0x20" name="2" cname="_USBDIV_2" sdcc_cname="_USBPLL_CLOCK_SRC_FROM_96MHZ_PLL_2" /> - </tqmask> + </mask> </config> - <config offset="0x1" name="CONFIG1H" wtqmask="0xFF" bvalue="0x05" > - <tqmask name="FOSC" value="0x0F" > + <config offset="0x1" name="CONFIG1H" wmask="0xFF" bvalue="0x05" > + <mask name="FOSC" value="0x0F" > <value value="0x00" name="XT" cname="_FOSC_XT_XT" sdcc_cname="_OSC_XT__USB_XT" /> <value value="0x01" name="XT" cname="_FOSC_XT_XT" sdcc_cname="_OSC_XT__USB_XT" /> <value value="0x02" name="XTPLL" cname="_FOSC_XTPLL" sdcc_cname="_OSC_XT__XT_PLL__USB_XT" /> @@ -74,46 +74,46 @@ <value value="0x0D" name="HS" cname="_FOSC_HS" sdcc_cname="_OSC_HS__USB_HS" /> <value value="0x0E" name="HSPLL" cname="_FOSC_HSPLL_HS" sdcc_cname="_OSC_HS__HS_PLL__USB_HS" /> <value value="0x0F" name="HSPLL" cname="_FOSC_HSPLL_HS" sdcc_cname="_OSC_HS__HS_PLL__USB_HS" /> - </tqmask> - <tqmask name="FCMEN" value="0x40" > + </mask> + <mask name="FCMEN" value="0x40" > <value value="0x00" name="Off" cname="_FCMEM_OFF" sdcc_cname="_FCMEN_OFF" /> <value value="0x40" name="On" cname="_FCMEM_ON" sdcc_cname="_FCMEN_ON" /> - </tqmask> - <tqmask name="IESO" value="0x80" > + </mask> + <mask name="IESO" value="0x80" > <value value="0x00" name="Off" cname="_IESO_OFF" /> <value value="0x80" name="On" cname="_IESO_ON" /> - </tqmask> + </mask> </config> - <config offset="0x2" name="CONFIG2L" wtqmask="0xFF" bvalue="0x1F" > - <tqmask name="PWRTE" value="0x01" > + <config offset="0x2" name="CONFIG2L" wmask="0xFF" bvalue="0x1F" > + <mask name="PWRTE" value="0x01" > <value value="0x00" name="On" cname="_PWRT_ON" sdcc_cname="_PUT_ON" /> <value value="0x01" name="Off" cname="_PWRT_OFF" sdcc_cname="_PUT_OFF" /> - </tqmask> - <tqmask name="BODEN" value="0x06" > + </mask> + <mask name="BODEN" value="0x06" > <value value="0x00" name="Off" cname="_BOR_OFF" sdcc_cname="_BODEN_OFF" /> <value value="0x02" name="Software" cname="_BOR_SOFT" sdcc_cname="_BODEN_CONTROLLED_WITH_SBOREN_BIT" /> <value value="0x04" name="On_run" cname="_BOR_ON_ACTIVE" sdcc_cname="_BODEN_ON_WHILE_ACTIVE" /> <value value="0x06" name="On" cname="_BOR_ON" sdcc_cname="_BODEN_ON" /> - </tqmask> - <tqmask name="BORV" value="0x18" > + </mask> + <mask name="BORV" value="0x18" > <value value="0x00" name="4.5" cname="_BORV_0" sdcc_cname="_BODENV_4_5V" /> <value value="0x08" name="4.2" cname="_BORV_1" sdcc_cname="_BODENV_4_2V" /> <value value="0x10" name="2.7" cname="_BORV_2" sdcc_cname="_BODENV_2_7V" /> <value value="0x18" name="2.0" cname="_BORV_3" sdcc_cname="_BODENV_2_0V" /> - </tqmask> - <tqmask name="VREGEN" value="0x20" > + </mask> + <mask name="VREGEN" value="0x20" > <value value="0x00" name="Off" cname="_VREGEN_OFF" /> <value value="0x20" name="On" cname="_VREGEN_ON" /> - </tqmask> + </mask> </config> - <config offset="0x3" name="CONFIG2H" wtqmask="0xFF" bvalue="0x1F" > - <tqmask name="WDT" value="0x01" > + <config offset="0x3" name="CONFIG2H" wmask="0xFF" bvalue="0x1F" > + <mask name="WDT" value="0x01" > <value value="0x00" name="Off" cname="_WDT_OFF" sdcc_cname="_WDT_DISABLED_CONTROLLED" /> <value value="0x01" name="On" cname="_WDT_ON" sdcc_cname="_WDT_ON" /> - </tqmask> - <tqmask name="WDTPS" value="0x1E" > + </mask> + <mask name="WDTPS" value="0x1E" > <value value="0x00" name="1:1" cname="_WDTPS_1" sdcc_cname="_WDTPS_1_1" /> <value value="0x02" name="1:2" cname="_WDTPS_2" sdcc_cname="_WDTPS_1_2" /> <value value="0x04" name="1:4" cname="_WDTPS_4" sdcc_cname="_WDTPS_1_4" /> @@ -130,135 +130,135 @@ <value value="0x1A" name="1:8192" cname="_WDTPS_8192" sdcc_cname="_WDTPS_1_8192" /> <value value="0x1C" name="1:16384" cname="_WDTPS_16384" sdcc_cname="_WDTPS_1_16384" /> <value value="0x1E" name="1:32768" cname="_WDTPS_32768" sdcc_cname="_WDTPS_1_32768" /> - </tqmask> + </mask> </config> - <config offset="0x4" name="CONFIG3L" wtqmask="0xFF" bvalue="0x00" /> + <config offset="0x4" name="CONFIG3L" wmask="0xFF" bvalue="0x00" /> - <config offset="0x5" name="CONFIG3H" wtqmask="0xFF" bvalue="0x83" ctqmask="0x01" > - <tqmask name="CCP2MX" value="0x01" > + <config offset="0x5" name="CONFIG3H" wmask="0xFF" bvalue="0x83" cmask="0x01" > + <mask name="CCP2MX" value="0x01" > <value value="0x00" name="RB3" cname="_CCP2MX_OFF" sdcc_cname="_CCP2MUX_RB3" /> <value value="0x01" name="RC1" cname="_CCP2MX_ON" sdcc_cname="_CCP2MUX_RC1" /> - </tqmask> - <tqmask name="PBADEN" value="0x02" > + </mask> + <mask name="PBADEN" value="0x02" > <value value="0x00" name="digital" cname="_PBADEN_OFF" sdcc_cname="_PBADEN_PORTB_4_0__CONFIGURED_AS_DIGITAL_I_O_ON_RESET" /> <value value="0x02" name="analog" cname="_PBADEN_ON" sdcc_cname="_PBADEN_PORTB_4_0__CONFIGURED_AS_ANALOG_INPUTS_ON_RESET" /> - </tqmask> - <tqmask name="LPT1OSC" value="0x04" > + </mask> + <mask name="LPT1OSC" value="0x04" > <value value="0x00" name="Off" cname="_LPT1OSC_OFF" /> <value value="0x04" name="On" cname="_LPT1OSC_ON" /> - </tqmask> - <tqmask name="MCLRE" value="0x80" > + </mask> + <mask name="MCLRE" value="0x80" > <value value="0x00" name="Internal" cname="_MCLRE_OFF" sdcc_cname="_MCLRE_MCLR_OFF_RE3_ON" /> <value value="0x80" name="External" cname="_MCLRE_ON" sdcc_cname="_MCLRE_MCLR_ON_RE3_OFF" /> - </tqmask> + </mask> </config> - <config offset="0x6" name="CONFIG4L" wtqmask="0xFF" bvalue="0x85" ctqmask="0x20" > - <tqmask name="STVREN" value="0x01" > + <config offset="0x6" name="CONFIG4L" wmask="0xFF" bvalue="0x85" cmask="0x20" > + <mask name="STVREN" value="0x01" > <value value="0x00" name="Off" cname="_STVREN_OFF" sdcc_cname="_STVR_OFF" /> <value value="0x01" name="On" cname="_STVREN_ON" sdcc_cname="_STVR_ON" /> - </tqmask> - <tqmask name="LVP" value="0x04" > + </mask> + <mask name="LVP" value="0x04" > <value value="0x00" name="Off" cname="_LVP_OFF" /> <value value="0x04" name="On" cname="_LVP_ON" /> - </tqmask> - <tqmask name="ICPORT" value="0x20" > + </mask> + <mask name="ICPORT" value="0x20" > <value value="0x00" name="Off" cname="_ICPRT_OFF" sdcc_cname="_ENICPORT_OFF" /> <value value="0x20" name="On" cname="_ICPRT_ON" sdcc_cname="_ENICPORT_ON" /> - </tqmask> - <tqmask name="XINST" value="0x40" > + </mask> + <mask name="XINST" value="0x40" > <value value="0x00" name="Off" cname="_XINST_OFF" sdcc_cname="_ENHCPU_OFF" /> <value value="0x40" name="On" cname="_XINST_ON" sdcc_cname="_ENHCPU_ON" /> - </tqmask> - <tqmask name="DEBUG" value="0x80" > + </mask> + <mask name="DEBUG" value="0x80" > <value value="0x00" name="On" cname="_DEBUG_ON" sdcc_cname="_BACKBUG_ON" /> <value value="0x80" name="Off" cname="_DEBUG_OFF" sdcc_cname="_BACKBUG_OFF" /> - </tqmask> + </mask> </config> - <config offset="0x7" name="CONFIG4H" wtqmask="0xFF" bvalue="0x00" /> + <config offset="0x7" name="CONFIG4H" wmask="0xFF" bvalue="0x00" /> - <config offset="0x8" name="CONFIG5L" wtqmask="0xFF" bvalue="0x0F" > - <tqmask name="CP_0" value="0x01" > + <config offset="0x8" name="CONFIG5L" wmask="0xFF" bvalue="0x0F" > + <mask name="CP_0" value="0x01" > <value value="0x00" name="0800:1FFF" cname="_CP0_ON" sdcc_cname="_CP_0_ON" /> <value value="0x01" name="Off" cname="_CP0_OFF" sdcc_cname="_CP_0_OFF" /> - </tqmask> - <tqmask name="CP_1" value="0x02" > + </mask> + <mask name="CP_1" value="0x02" > <value value="0x00" name="2000:3FFF" cname="_CP1_ON" sdcc_cname="_CP_1_ON" /> <value value="0x02" name="Off" cname="_CP1_OFF" sdcc_cname="_CP_1_OFF" /> - </tqmask> - <tqmask name="CP_2" value="0x04" > + </mask> + <mask name="CP_2" value="0x04" > <value value="0x00" name="4000:5FFF" cname="_CP2_ON" sdcc_cname="_CP_2_ON" /> <value value="0x04" name="Off" cname="_CP2_OFF" sdcc_cname="_CP_2_OFF" /> - </tqmask> - <tqmask name="CP_3" value="0x08" > + </mask> + <mask name="CP_3" value="0x08" > <value value="0x00" name="6000:7FFF" cname="_CP3_ON" sdcc_cname="_CP_3_ON" /> <value value="0x08" name="Off" cname="_CP3_OFF" sdcc_cname="_CP_3_OFF" /> - </tqmask> + </mask> </config> - <config offset="0x9" name="CONFIG5H" wtqmask="0xFF" bvalue="0x40" > - <tqmask name="CPB" value="0x40" > + <config offset="0x9" name="CONFIG5H" wmask="0xFF" bvalue="0x40" > + <mask name="CPB" value="0x40" > <value value="0x00" name="0000:07FF" cname="_CPB_ON" /> <value value="0x40" name="Off" cname="_CPB_OFF" /> - </tqmask> + </mask> </config> - <config offset="0xA" name="CONFIG6L" wtqmask="0xFF" bvalue="0x0F" > - <tqmask name="WRT_0" value="0x01" > + <config offset="0xA" name="CONFIG6L" wmask="0xFF" bvalue="0x0F" > + <mask name="WRT_0" value="0x01" > <value value="0x00" name="0800:1FFF" cname="_WRT0_ON" sdcc_cname="_WRT_0_ON" /> <value value="0x01" name="Off" cname="_WRT0_OFF" sdcc_cname="_WRT_0_OFF" /> - </tqmask> - <tqmask name="WRT_1" value="0x02" > + </mask> + <mask name="WRT_1" value="0x02" > <value value="0x00" name="2000:3FFF" cname="_WRT1_ON" sdcc_cname="_WRT_1_ON" /> <value value="0x02" name="Off" cname="_WRT1_OFF" sdcc_cname="_WRT_1_OFF" /> - </tqmask> - <tqmask name="WRT_2" value="0x04" > + </mask> + <mask name="WRT_2" value="0x04" > <value value="0x00" name="4000:5FFF" cname="_WRT2_ON" sdcc_cname="_WRT_2_ON" /> <value value="0x04" name="Off" cname="_WRT2_OFF" sdcc_cname="_WRT_2_OFF" /> - </tqmask> - <tqmask name="WRT_3" value="0x08" > + </mask> + <mask name="WRT_3" value="0x08" > <value value="0x00" name="6000:7FFF" cname="_WRT3_ON" sdcc_cname="_WRT_3_ON" /> <value value="0x08" name="Off" cname="_WRT3_OFF" sdcc_cname="_WRT_3_OFF" /> - </tqmask> + </mask> </config> - <config offset="0xB" name="CONFIG6H" wtqmask="0xFF" bvalue="0x60" ctqmask="0x40" > - <tqmask name="WRTC" value="0x20" > + <config offset="0xB" name="CONFIG6H" wmask="0xFF" bvalue="0x60" cmask="0x40" > + <mask name="WRTC" value="0x20" > <value value="0x00" name="All" cname="_WRTC_ON" /> <value value="0x20" name="Off" cname="_WRTC_OFF" /> - </tqmask> - <tqmask name="WRTB" value="0x40" > + </mask> + <mask name="WRTB" value="0x40" > <value value="0x00" name="0000:07FF" cname="_WRTB_ON" /> <value value="0x40" name="Off" cname="_WRTB_OFF" /> - </tqmask> + </mask> </config> - <config offset="0xC" name="CONFIG7L" wtqmask="0xFF" bvalue="0x0F" > - <tqmask name="EBTR_0" value="0x01" > + <config offset="0xC" name="CONFIG7L" wmask="0xFF" bvalue="0x0F" > + <mask name="EBTR_0" value="0x01" > <value value="0x00" name="0800:1FFF" cname="_EBTR0_ON" sdcc_cname="_EBTR_0_ON" /> <value value="0x01" name="Off" cname="_EBTR0_OFF" sdcc_cname="_EBTR_0_OFF" /> - </tqmask> - <tqmask name="EBTR_1" value="0x02" > + </mask> + <mask name="EBTR_1" value="0x02" > <value value="0x00" name="2000:3FFF" cname="_EBTR1_ON" sdcc_cname="_EBTR_1_ON" /> <value value="0x02" name="Off" cname="_EBTR1_OFF" sdcc_cname="_EBTR_1_OFF" /> - </tqmask> - <tqmask name="EBTR_2" value="0x04" > + </mask> + <mask name="EBTR_2" value="0x04" > <value value="0x00" name="4000:5FFF" cname="_EBTR2_ON" sdcc_cname="_EBTR_2_ON" /> <value value="0x04" name="Off" cname="_EBTR2_OFF" sdcc_cname="_EBTR_2_OFF" /> - </tqmask> - <tqmask name="EBTR_3" value="0x08" > + </mask> + <mask name="EBTR_3" value="0x08" > <value value="0x00" name="6000:7FFF" cname="_EBTR3_ON" sdcc_cname="_EBTR_3_ON" /> <value value="0x08" name="Off" cname="_EBTR3_OFF" sdcc_cname="_EBTR_3_OFF" /> - </tqmask> + </mask> </config> - <config offset="0xD" name="CONFIG7H" wtqmask="0xFF" bvalue="0x40" > - <tqmask name="EBTRB" value="0x40" > + <config offset="0xD" name="CONFIG7H" wmask="0xFF" bvalue="0x40" > + <mask name="EBTRB" value="0x40" > <value value="0x00" name="0000:07FF" cname="_EBTRB_ON" /> <value value="0x40" name="Off" cname="_EBTRB_OFF" /> - </tqmask> + </mask> </config> <!--* Packages *************************************************************--> |