diff options
| author | Timothy Pearson <kb9vqf@pearsoncomputing.net> | 2014-01-10 23:13:22 -0600 |
|---|---|---|
| committer | Timothy Pearson <kb9vqf@pearsoncomputing.net> | 2014-01-10 23:13:22 -0600 |
| commit | 0ffb793cb56ec10a43ae241299b347bc4fef7b5c (patch) | |
| tree | 19a1f24d715f08da35f137c4b80c5bd1d58e65fa /fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise | |
| parent | 37420cfb78718d7a7ac9bfde754fbd62c6d29f2c (diff) | |
| download | ulab-0ffb793cb56ec10a43ae241299b347bc4fef7b5c.tar.gz ulab-0ffb793cb56ec10a43ae241299b347bc4fef7b5c.zip | |
Relayout the GUI to be more in line with expected norms
Add user logic reset signal
Stabilize data transfer
Diffstat (limited to 'fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise')
| -rw-r--r-- | fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise index f418fb2..565fe9a 100644 --- a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise +++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise @@ -326,6 +326,7 @@ <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> + <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> |