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authorTimothy Pearson <kb9vqf@pearsoncomputing.net>2014-01-09 21:16:28 -0600
committerTimothy Pearson <kb9vqf@pearsoncomputing.net>2014-01-09 21:16:28 -0600
commit04ab7c66320d2f4601626c3018e4ac9fceb4a75c (patch)
tree88719528521157f8ce2da53d419a2e422bed6907 /fpga/xilinx
parent963b88fb0bb3a20bd4b6eb3d73095172a3760d55 (diff)
downloadulab-04ab7c66320d2f4601626c3018e4ac9fceb4a75c.tar.gz
ulab-04ab7c66320d2f4601626c3018e4ac9fceb4a75c.zip
Add initial GOMC compatible uLab debug system hardware design files
Diffstat (limited to 'fpga/xilinx')
l---------fpga/xilinx/digilent/spartan_3/remote_access.v1
l---------fpga/xilinx/digilent/spartan_3e/remote_access.v1
l---------fpga/xilinx/digilent/spartan_6/remote_access.v1
-rw-r--r--fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v33
-rw-r--r--fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.ucf8
-rw-r--r--fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v330
l---------fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/remote_access.v1
-rw-r--r--fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/s6_remotefpga_test.xise366
8 files changed, 0 insertions, 741 deletions
diff --git a/fpga/xilinx/digilent/spartan_3/remote_access.v b/fpga/xilinx/digilent/spartan_3/remote_access.v
deleted file mode 120000
index ccde8db..0000000
--- a/fpga/xilinx/digilent/spartan_3/remote_access.v
+++ /dev/null
@@ -1 +0,0 @@
-../../../common/remote_access.v \ No newline at end of file
diff --git a/fpga/xilinx/digilent/spartan_3e/remote_access.v b/fpga/xilinx/digilent/spartan_3e/remote_access.v
deleted file mode 120000
index ccde8db..0000000
--- a/fpga/xilinx/digilent/spartan_3e/remote_access.v
+++ /dev/null
@@ -1 +0,0 @@
-../../../common/remote_access.v \ No newline at end of file
diff --git a/fpga/xilinx/digilent/spartan_6/remote_access.v b/fpga/xilinx/digilent/spartan_6/remote_access.v
deleted file mode 120000
index ccde8db..0000000
--- a/fpga/xilinx/digilent/spartan_6/remote_access.v
+++ /dev/null
@@ -1 +0,0 @@
-../../../common/remote_access.v \ No newline at end of file
diff --git a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v
deleted file mode 100644
index 7c9fcb0..0000000
--- a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/data_storage.v
+++ /dev/null
@@ -1,33 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-//
-// (c) 2013 Timothy Pearson, Raptor Engineering
-// Released into the Public Domain
-//
-//////////////////////////////////////////////////////////////////////////////////
-
-module data_storage(
- input clka,
- input [7:0] dina,
- input [(RAM_ADDR_BITS-1):0] addra,
- input wea,
- output reg [7:0] douta);
-
- parameter RAM_ADDR_BITS = 14;
- parameter RAM_WIDTH = 8;
-
- // Xilinx specific directive
- (* RAM_STYLE="BLOCK" *)
-
- reg [RAM_WIDTH-1:0] data_storage_ram [(2**RAM_ADDR_BITS)-1:0];
-
- always @(posedge clka) begin
- if (wea) begin
- data_storage_ram[addra] <= dina;
- douta <= dina;
- end else begin
- douta <= data_storage_ram[addra];
- end
- end
-
-endmodule
diff --git a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.ucf b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.ucf
deleted file mode 100644
index c9a68dd..0000000
--- a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.ucf
+++ /dev/null
@@ -1,8 +0,0 @@
-# (c) 2013 Timothy Pearson, Raptor Engineering
-# Released into the Public Domain
-
-NET "clk" LOC = "V10" | IOSTANDARD = "LVCMOS33";
-TIMESPEC TS_clk = PERIOD clk 100000 kHz;
-
-NET "serial_input" LOC = "T12" | IOSTANDARD = "LVCMOS33";
-NET "serial_output" LOC = "M10" | IOSTANDARD = "LVCMOS33";
diff --git a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v
deleted file mode 100644
index b852a6d..0000000
--- a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v
+++ /dev/null
@@ -1,330 +0,0 @@
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: Raptor Engineering
-// Engineer: Timothy Pearson
-//
-// Design Name: Remote Access Sample Design
-// Module Name: sample_demo
-// Project Name: Remote Access Sample Design
-// Target Devices: Any
-// Description: Remote Access Sample Design
-//
-// Dependencies:
-//
-// (c) 2007-2013 Timothy Pearson, Raptor Engineering
-// Released into the Public Domain
-//
-//////////////////////////////////////////////////////////////////////////////////
-module main(
- input clk, // 100MHz clock
-
- // Serial port
- input serial_input,
- output serial_output);
-
- parameter RAM_ADDR_BITS = 14;
-
- wire [7:0] four_bit_output; // Output from the user program to the remote access module
- wire [7:0] four_bit_input; // Input to the user program from the remote access module
- wire [7:0] eight_bit_output; // Output from the user program to the remote access module
- wire [7:0] eight_bit_input; // Input to the user program from the remote access module
- wire [15:0] sixteen_bit_output; // Output from the user program to the remote access module
- wire [15:0] sixteen_bit_input; // Input to the user program from the remote access module
-
- wire [7:0] remote_access_local_input;
-
- reg [7:0] serial_data_to_write;
- wire sieze_serial_tx;
- reg serial_tx_strobe = 0;
- wire serial_data_received;
- wire serial_rx_strobe;
-
- wire [5:0] lcd_data_in_address;
- wire [7:0] lcd_data_in_data;
- wire lcd_data_in_enable;
-
- wire [7:0] led_segment_bus;
- wire [3:0] led_digit_select;
-
- //-------------------------------------------------------------------------------------------------------
- //
- // Generate a 50MHz clock for the remote access module
- //
- //-------------------------------------------------------------------------------------------------------
-
- reg main_fifty_clock = 0;
- always @(posedge clk) begin
- main_fifty_clock = !main_fifty_clock;
- end
-
- //-------------------------------------------------------------------------------------------------------
- //
- // Generate a 25MHz clock for the user progam
- //
- //-------------------------------------------------------------------------------------------------------
-
- reg clk_div_by_two = 0;
- always @(posedge main_fifty_clock) begin
- clk_div_by_two = !clk_div_by_two;
- end
-
- //-------------------------------------------------------------------------------------------------------
- //
- // Remote Access Module
- //
- // Inputs:
- // .clk: 50MHz clock
- // .four_bit_input 4-bit input to the user program from the remote access module
- // .eight_bit_input 8-bit input to the user program from the remote access module
- // .sixteen_bit_input 16-bit input to the user program from the remote access module
- // .serial_port_receiver Input from the serial port's RxD (receive data) pin
- // .remote_access_input_enable Toggle remote access input vs. local input mode
- // .local_input Local input to the remote program
- // .seize_serial_tx Sieze control of the serial transmitter from the remote control system
- // .serial_tx_data Byte to be transmitted on transmit strobe if control has been siezed
- // .serial_tx_strobe Transmit serial data on posedge if transmit control has been siezed
- // .lcd_data_in_address LCD character address (0-32) to write character code to
- // .lcd_data_in_data LCD character code to write to the address specified
- // .lcd_data_in_enable Enable LCD data write
- // .sram_wren_in Synchronous SRAM write enable (1=write, 0=read)
- // .sram_clock_in Synchronous SRAM clock input
- // .sram_data_in Synchronous SRAM data input (8-bit)
- // .sram_address_in Synchronous SRAM address input (14-bit by default)
- // .sram_processing_done When 1, signal release of user control of synchronous SRAM
- // .led_segment_bus Connect directly to the 8 bits controlling the LED display segments
- // .led_digit_select Connect directly to the 4 bits enabling the LED display digits
- //
- // Outputs:
- // .four_bit_output 4-bit output from the user program to the remote access module
- // .eight_bit_output 8-bit output from the user program to the remote access module
- // .sixteen_bit_output 16-bit output from the user program to the remote access module
- // .lcd_data_out Data output to the LCD
- // .lcd_rs_out RS signal output to the LCD
- // .lcd_rw_out RW signal output to the LCD
- // .lcd_enable_out ENABLE signal output to the LCD
- // .serial_port_transmitter Output to the serial port's TxD (transmit data) pin
- // .serial_rx_data The last received serial data
- // .serial_rx_strobe Recevied serial data valid while this signal is 1
- // .sram_data_out Synchronous SRAM data output (8-bit)
- // .sram_available Synchronous SRAM under user control
- //
- //-------------------------------------------------------------------------------------------------------
-
- wire sram_wren_in;
- wire sram_clock_in;
- wire [7:0] sram_data_in;
- wire [(RAM_ADDR_BITS-1):0] sram_address_in;
- wire [7:0] sram_data_out;
- wire sram_available;
- wire sram_processing_done;
-
- // Uncomment this block if no image processing module is provided
- // assign sram_wren_in = 0;
- // assign sram_data_in = 0;
- // assign sram_address_in = 0;
- // assign sram_processing_done = 1;
-
- assign sram_clock_in = main_fifty_clock;
-
- remote_access #(RAM_ADDR_BITS) remote_access(.main_fifty_clock(main_fifty_clock), .remote_access_4_bit_output(four_bit_output),
- .remote_access_4_bit_input(four_bit_input), .remote_access_8_bit_output(eight_bit_output),
- .remote_access_8_bit_input(eight_bit_input), .remote_access_16_bit_output(sixteen_bit_output),
- .remote_access_16_bit_input(sixteen_bit_input),
- .serial_port_receiver(serial_input), .serial_port_transmitter(serial_output), .remote_access_input_enable(btn_center),
- .local_input(remote_access_local_input), .seize_serial_tx(sieze_serial_tx), .serial_tx_data(serial_data_to_write),
- .serial_tx_strobe(serial_tx_strobe), .serial_rx_data(serial_data_received), .serial_rx_strobe(serial_rx_strobe),
- .lcd_data_in_address(lcd_data_in_address), .lcd_data_in_data(lcd_data_in_data), .lcd_data_in_enable(lcd_data_in_enable),
- .sram_wren_in(sram_wren_in), .sram_clock_in(sram_clock_in), .sram_data_in(sram_data_in), .sram_address_in(sram_address_in),
- .sram_data_out(sram_data_out), .sram_available(sram_available), .sram_processing_done(sram_processing_done),
- .led_segment_bus(led_segment_bus), .led_digit_select(led_digit_select));
-
- assign remote_access_local_input[7:4] = 0; // Local inputs
- assign remote_access_local_input[3:0] = 0; // Local inputs
- assign led_bank = eight_bit_input; // Mirror input to the LEDs
- assign sieze_serial_tx = 0; // Allow the remote control module to use the serial port
- // If the user module must access the serial port directly, delete
- // this assign statement and control this wire with your module.
-
- //-------------------------------------------------------------------------------------------------------
- //
- // User Module Instantiation
- //
- // Instantiate the simple user module to display remote access input values on the LEDs and to feed
- // button presses to the remote access module. The 16-bit remote access lines are in loopback.
- // Feel free to delete this instantiation and the module below to replace it with your module.
- //
- //-------------------------------------------------------------------------------------------------------
-
- sample_demo sample_demo(.clk(clk_div_by_two), .four_bit_input(four_bit_input), .four_bit_output(four_bit_output),
- .eight_bit_input(eight_bit_input), .eight_bit_output(eight_bit_output), .sixteen_bit_input(sixteen_bit_input),
- .sixteen_bit_output(sixteen_bit_output), .lcd_data_in_address(lcd_data_in_address),
- .lcd_data_in_data(lcd_data_in_data), .lcd_data_in_enable(lcd_data_in_enable),
- .led_segment_bus(led_segment_bus), .led_digit_select(led_digit_select));
-
- //-------------------------------------------------------------------------------------------------------
- //
- // User Image Processing Module Instantiation
- //
- // Instantiate the simple userimage processing module to invert the bits in any images sent to the FPGA
- //
- //-------------------------------------------------------------------------------------------------------
-
- sample_image_processing_demo sample_image_processing_demo(.clk(clk_div_by_two), .wren(sram_wren_in), .dout(sram_data_in), .addr(sram_address_in),
- .din(sram_data_out), .enable(sram_available), .done(sram_processing_done));
-
-endmodule
-
-//-------------------------------------------------------------------------------------------------------
-//
-// Demo User Module
-//
-//-------------------------------------------------------------------------------------------------------
-
-module sample_demo(clk, four_bit_input, four_bit_output, eight_bit_input, eight_bit_output, sixteen_bit_input, sixteen_bit_output, lcd_data_in_address, lcd_data_in_data, lcd_data_in_enable, led_segment_bus, led_digit_select);
- input clk;
-
- input [3:0] four_bit_input;
- output reg [3:0] four_bit_output;
- input [7:0] eight_bit_input;
- output reg [7:0] eight_bit_output;
- input [15:0] sixteen_bit_input;
- output reg [15:0] sixteen_bit_output;
-
- output reg [5:0] lcd_data_in_address;
- output reg [7:0] lcd_data_in_data;
- output reg lcd_data_in_enable;
-
- output reg [7:0] led_segment_bus;
- output reg [3:0] led_digit_select;
-
- reg [7:0] lcd_sample_counter = 48; // Create a sample LCD display counter register
- reg [31:0] lcd_character_change_timer = 0; // Wait a certain number of cycles before loading a new character
- reg [5:0] lcd_current_character = 0; // The current character's address
-
- always @(posedge clk) begin
- four_bit_output = four_bit_input; // Loopback
- eight_bit_output = eight_bit_input[3:0] + eight_bit_input[7:4]; // Sample adder
- sixteen_bit_output = sixteen_bit_input[15:8] * sixteen_bit_input[7:0]; // Sample multiplier
-
- // Sample LCD display routine
- lcd_data_in_address = lcd_current_character; // Character location on the LCD display
- lcd_data_in_data = lcd_sample_counter; // Character code to display
- lcd_data_in_enable = 1; // Enable data transmission
-
- // Cycle through all character positions
- lcd_current_character = lcd_current_character + 1;
- if (lcd_current_character > 31) begin
- lcd_current_character = 16;
- end
-
- // Cycle through the numbers 0 to 9 at one second intervals
- lcd_character_change_timer = lcd_character_change_timer + 1;
- if (lcd_character_change_timer > 25000000) begin // Wait one second in between character changes
- lcd_character_change_timer = 0;
- lcd_sample_counter = lcd_sample_counter + 1;
- if (lcd_sample_counter > 57) begin // Character code for the digit 9
- lcd_sample_counter = 48; // Character code for the digit 0
- end
- end
- end
-
- // 7-segment LED display driver clock generator
- reg sseg_clock;
- reg [4:0] sseg_clock_counter;
-
- always @(posedge clk) begin
- sseg_clock_counter = sseg_clock_counter + 1;
- if (sseg_clock_counter > 16) begin
- sseg_clock_counter = 0;
- sseg_clock = ~sseg_clock;
- end
- end
-
- // 7-segment LED display driver
- // led_segment_bus and led_digit_select are active low
- // The bit sequence, MSB to LSB, is dp a b c d e f g
- // Segment letters are taken from ug130.pdf page 15
-
- // 0: 8'b10000001
- // 1: 8'b11001111
- // 2: 8'b10010010
- // 3: 8'b10000110
- reg [2:0] current_anode;
- always @(posedge sseg_clock) begin
- current_anode = current_anode + 1;
- if (current_anode > 3) begin
- current_anode = 0;
- end
-
- case (current_anode)
- 0: begin
- led_digit_select = 4'b1110;
- led_segment_bus = 8'b10000001;
- end
- 1: begin
- led_digit_select = 4'b1101;
- led_segment_bus = 8'b11001111;
- end
- 2: begin
- led_digit_select = 4'b1011;
- led_segment_bus = 8'b10010010;
- end
- 3: begin
- led_digit_select = 4'b0111;
- led_segment_bus = 8'b10000110;
- end
- endcase
- end
-endmodule
-
-//-------------------------------------------------------------------------------------------------------
-//
-// Demo User Image Processing Module
-//
-//-------------------------------------------------------------------------------------------------------
-
-module sample_image_processing_demo(clk, wren, dout, addr, din, enable, done);
- parameter IMAGE_RAM_ADDR_BITS = 14;
-
- input clk;
-
- output reg wren;
- output reg [7:0] dout;
- output reg [(IMAGE_RAM_ADDR_BITS-1):0] addr;
- input [7:0] din;
- input enable;
- output reg done;
-
- reg prev_enable;
- reg [IMAGE_RAM_ADDR_BITS:0] counter;
- reg toggler;
-
- always @(posedge clk) begin
- if ((enable == 1) && (prev_enable == 0)) begin
- counter = 0;
- toggler = 0;
- end
- if ((enable == 1) && (done == 0)) begin
- if (toggler == 0) begin
- wren = 0;
- addr = counter;
- toggler = 1;
- end else begin
- dout = ~din;
- wren = 1;
- addr = counter;
- counter = counter + 1;
- if (counter > (2**IMAGE_RAM_ADDR_BITS)) begin
- done = 1;
- end
- toggler = 0;
- end
- end
- if (enable == 0) begin
- done = 0;
- addr = 0;
- toggler = 0;
- end
- prev_enable = enable;
- end
-endmodule
diff --git a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/remote_access.v b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/remote_access.v
deleted file mode 120000
index a018632..0000000
--- a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/remote_access.v
+++ /dev/null
@@ -1 +0,0 @@
-../remote_access.v \ No newline at end of file
diff --git a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/s6_remotefpga_test.xise b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/s6_remotefpga_test.xise
deleted file mode 100644
index 45b9e22..0000000
--- a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/s6_remotefpga_test.xise
+++ /dev/null
@@ -1,366 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="remote_access.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
- </file>
- <file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
- </file>
- <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- </file>
- <file xil_pn:name="data_storage.v" xil_pn:type="FILE_VERILOG">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
- </file>
- </files>
-
- <properties>
- <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
- <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
- <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
- <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
- <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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- <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
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- <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
- <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
- <property xil_pn:name="Target UCF File Name" xil_pn:value="main.ucf" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
- <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
- <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
- <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
- <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
- <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
- <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
- <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_DesignName" xil_pn:value="s6_remotefpga_test" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-03-03T01:45:17" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6E464769C51A5363CC11E7DB5F4485BE" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings/>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- </autoManagedFiles>
-
-</project>