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| author | Timothy Pearson <kb9vqf@pearsoncomputing.net> | 2013-10-30 13:23:45 -0500 |
|---|---|---|
| committer | Timothy Pearson <kb9vqf@pearsoncomputing.net> | 2013-10-30 13:23:45 -0500 |
| commit | 8ce60c7f5244a905d466450b762e18620cccfad8 (patch) | |
| tree | d4abf646299ef8b10c5e88c10c085a6ba61919dc /fpga | |
| parent | f27e0f01840bcc42e521beb29b4f5964b1649bda (diff) | |
| download | ulab-8ce60c7f5244a905d466450b762e18620cccfad8.tar.gz ulab-8ce60c7f5244a905d466450b762e18620cccfad8.zip | |
Fix prior commit
Diffstat (limited to 'fpga')
| -rw-r--r-- | fpga/common/remote_access.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/fpga/common/remote_access.v b/fpga/common/remote_access.v index c323097..5a37e86 100644 --- a/fpga/common/remote_access.v +++ b/fpga/common/remote_access.v @@ -403,7 +403,7 @@ module remote_access( tx_toggle = 1; transmit_dsp_status_counter = transmit_dsp_status_counter + 1; - data_storage_addra_reg = transmit_dsp_status_counter; + data_storage_addra_reg = transmit_dsp_status_counter[(RAM_ADDR_BITS-1):0]; if (transmit_dsp_status_counter >= (2**RAM_ADDR_BITS)) begin transmit_dsp_status_done = 1; data_storage_write_enable_reg = 1'bz; @@ -474,7 +474,7 @@ module remote_access( reg [7:0] serial_command_timer = 0; reg update_lcd_display = 0; reg [7:0] serial_update_counter = 0; - reg [15:0] dsp_update_counter = 0; + reg [RAM_ADDR_BITS:0] dsp_update_counter = 0; reg [7:0] received_lcd_display_string [31:0]; reg data_write_timer = 0; reg waiting_on_dsp_processing = 0; @@ -604,7 +604,7 @@ module remote_access( // DSP input data if (dsp_update_counter < (2**RAM_ADDR_BITS)) begin data_storage_remote_enable = 1; - data_storage_addra_reg = dsp_update_counter; + data_storage_addra_reg = dsp_update_counter[(RAM_ADDR_BITS-1):0]; data_storage_dina_reg = serial_rx_data_reg; data_storage_write_enable_reg = 1; data_write_timer = 3; |