diff options
| -rw-r--r-- | clients/tde/src/part/fpgaview/part.cpp | 9 | ||||
| -rw-r--r-- | fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v | 10 |
2 files changed, 13 insertions, 6 deletions
diff --git a/clients/tde/src/part/fpgaview/part.cpp b/clients/tde/src/part/fpgaview/part.cpp index b40f167..7ddec7d 100644 --- a/clients/tde/src/part/fpgaview/part.cpp +++ b/clients/tde/src/part/fpgaview/part.cpp @@ -1251,7 +1251,7 @@ void FPGAViewPart::receiveInputStatesFromRemoteFPGA() { return; #define POLL_FOR_DATA_IMMEDIATE if (!m_updateTimer->isActive()) { \ - m_updateTimer->start(50, TRUE); \ + m_updateTimer->start(10, TRUE); \ } void FPGAViewPart::updateDisplay() { @@ -1598,7 +1598,6 @@ void FPGAViewPart::updateDisplay() { while (offset < m_dataMemorySize) { m_socket->readBlock(recData.data()+offset, 1024); offset = offset + 1024; - m_base->dataProcessingProgressBar->setProgress((m_dataMemorySize*2) + offset); } m_base->dataProcessingStatusLabel->setText(i18n("Writing data to file") + "..."); @@ -1657,6 +1656,12 @@ void FPGAViewPart::updateDisplay() { POLL_FOR_DATA_IMMEDIATE } else { + // Update the GUI with status information + m_base->dataProcessingProgressBar->setProgress(m_dataMemorySize + m_socket->bytesAvailable()); + if (m_socket->bytesAvailable() > 0) { + m_base->dataProcessingStatusLabel->setText(i18n("Receiving data from FPGA") + "..."); + } + if (!m_timeoutTimer->isActive()) { m_dataOutputFile->flush(); m_dataOutputFile->close(); diff --git a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v index 85c08be..9f37f9d 100644 --- a/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v +++ b/fpga/xilinx/digilent/spartan_6/s6_remotefpga_test/main.v @@ -284,17 +284,19 @@ endmodule //-------------------------------------------------------------------------------------------------------
module sample_image_processing_demo(clk, wren, dout, addr, din, enable, done);
+ parameter IMAGE_RAM_ADDR_BITS = 14;
+
input clk;
output reg wren;
output reg [7:0] dout;
- output reg [(RAM_ADDR_BITS-1):0] addr;
+ output reg [(IMAGE_RAM_ADDR_BITS-1):0] addr;
input [7:0] din;
input enable;
output reg done;
reg prev_enable;
- reg [(RAM_ADDR_BITS-1):0] counter;
+ reg [(IMAGE_RAM_ADDR_BITS-1):0] counter;
reg toggler;
always @(posedge clk) begin
@@ -312,7 +314,7 @@ module sample_image_processing_demo(clk, wren, dout, addr, din, enable, done); wren = 1;
addr = counter;
counter = counter + 1;
- if (counter > (2**RAM_ADDR_BITS)) begin
+ if (counter > (2**IMAGE_RAM_ADDR_BITS)) begin
done = 1;
end
toggler = 0;
@@ -325,4 +327,4 @@ module sample_image_processing_demo(clk, wren, dout, addr, din, enable, done); end
prev_enable = enable;
end
-endmodule
\ No newline at end of file +endmodule
|