1 files changed, 39 insertions, 14 deletions

diff --git a/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v b/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v
index 1dd957e..a68d800 100644
--- a/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v
+++ b/fpga/gpmc/xilinx/common/logic_analyzer_data_storage.v
@@ -7,38 +7,63 @@
 //////////////////////////////////////////////////////////////////////////////////
 
 module logic_analyzer_data_storage(
-	input clka,
-	input clkb,
-	input [63:0] dina,
-	input [63:0] dinb,
-	input [10:0] addra,
-	input [10:0] addrb,
+	input clk,
+	input [(RAM_WIDTH-1):0] dina,
+	input [(RAM_WIDTH-1):0] dinb,
+	input [(RAM_ADDR_BITS-1):0] addra,
+	input [(RAM_ADDR_BITS-1):0] addrb,
 	input wea,
 	input web,
-	output reg [63:0] douta,
-	output reg [63:0] doutb);
+	output reg [(RAM_WIDTH-1):0] douta,
+	output reg [(RAM_WIDTH-1):0] doutb);
 
+	parameter RAM_ADDR_BITS = 11;
 	parameter RAM_WIDTH = 64;
 	
 	// Xilinx specific directive
 	(* RAM_STYLE="BLOCK" *)
 	
-	reg [RAM_WIDTH-1:0] data_storage_ram [(2**11)-1:0];
-	
+	reg [RAM_WIDTH-1:0] logic_analyzer_data_storage_ram [(2**RAM_ADDR_BITS)-1:0];
+
+	// Initial RAM values for debugging
+	integer index;
+	initial begin
+		for (index = 0; index < ((2**RAM_ADDR_BITS)-1); index = index + 2) begin
+			logic_analyzer_data_storage_ram[index+0] = {(RAM_WIDTH/4){4'ha}};
+			logic_analyzer_data_storage_ram[index+1] = {(RAM_WIDTH/4){4'h5}};
+		end
+	end
+
+	// Registered
 	always @(posedge clka) begin
-		douta <= data_storage_ram[addra];
+		douta <= logic_analyzer_data_storage_ram[addra];
 		if (wea) begin
-			data_storage_ram[addra] <= dina;
+			logic_analyzer_data_storage_ram[addra] <= dina;
 			douta <= dina;
 		end
 	end
 
 	always @(posedge clkb) begin
-		doutb <= data_storage_ram[addrb];
+		doutb <= logic_analyzer_data_storage_ram[addrb];
 		if (web) begin
-			data_storage_ram[addrb] <= dinb;
+			logic_analyzer_data_storage_ram[addrb] <= dinb;
 			doutb <= dinb;
 		end
 	end
 
+// 	// Unregistered
+// 	always @(posedge clka) begin
+// 		if (wea) begin
+// 			logic_analyzer_data_storage_ram[addra] <= dina;
+// 		end
+// 	end
+// 	assign douta = logic_analyzer_data_storage_ram[addra];
+// 
+// 	always @(posedge clkb) begin
+// 		if (web) begin
+// 			logic_analyzer_data_storage_ram[addrb] <= dinb;
+// 		end
+// 	end
+// 	assign doutb = logic_analyzer_data_storage_ram[addrb];
+
 endmodule