diff options
Diffstat (limited to 'fpga/serial/common/remote_access.v')
| -rw-r--r-- | fpga/serial/common/remote_access.v | 31 |
1 files changed, 30 insertions, 1 deletions
diff --git a/fpga/serial/common/remote_access.v b/fpga/serial/common/remote_access.v index 3a52885..e30006f 100644 --- a/fpga/serial/common/remote_access.v +++ b/fpga/serial/common/remote_access.v @@ -18,6 +18,9 @@ // sales@raptorengineering.com // ////////////////////////////////////////////////////////////////////////////////// + +`include "remote_access_defines.v" + module remote_access( input main_fifty_clock, // 50MHz clock in input [3:0] remote_access_4_bit_output, // 4 bit output from the user program to remote access client @@ -38,13 +41,17 @@ module remote_access( input [5:0] lcd_data_in_address, input [7:0] lcd_data_in_data, input lcd_data_in_enable, +`ifdef SYSTEM_HAS_SRAM input sram_wren_in, input sram_clock_in, input [7:0] sram_data_in, input [(RAM_ADDR_BITS-1):0] sram_address_in, output [7:0] sram_data_out, +`endif output sram_available, +`ifdef SYSTEM_HAS_SRAM input sram_processing_done, +`endif input [7:0] led_segment_bus, input [3:0] led_digit_select, @@ -55,6 +62,10 @@ module remote_access( output remote_access_lcd_enable_out); parameter RAM_ADDR_BITS = 14; + +`ifndef SYSTEM_HAS_SRAM + reg sram_processing_done = 1'b1; +`endif reg [7:0] remote_access_4_bit_input_reg; reg [7:0] remote_access_8_bit_input_reg; @@ -184,7 +195,7 @@ module remote_access( led_display_bytes[3] = 255; end end - + //----------------------------------------------------------------------------------- // // Instantiate the data storage RAM for signal processing @@ -202,6 +213,7 @@ module remote_access( reg [(RAM_ADDR_BITS-1):0] data_storage_addra_reg; reg data_storage_write_enable_reg; +`ifdef SYSTEM_HAS_SRAM data_storage #(RAM_ADDR_BITS) data_storage(.clka(data_storage_clka), .dina(data_storage_dina), .addra(data_storage_addra), .wea(data_storage_write_enable), .douta(data_storage_data_out)); @@ -211,6 +223,7 @@ module remote_access( assign data_storage_write_enable = (data_storage_remote_enable) ? data_storage_write_enable_reg : sram_wren_in; assign sram_data_out = data_storage_data_out; +`endif // ----------------------------------------------------------------------------------------------- // @@ -396,11 +409,17 @@ module remote_access( if ((transmit_dsp_status == 1) && (transmit_dsp_rx_complete == 0) && (transmit_dsp_status_done == 0)) begin if (transmit_dsp_status_holdoff == 0) begin transmit_dsp_status_holdoff = 1; +`ifdef SYSTEM_HAS_SRAM data_storage_write_enable_reg = 0; data_storage_addra_reg = 0; // Initial data value +`endif end else begin +`ifdef SYSTEM_HAS_SRAM data_storage_write_enable_reg = 0; TxD_data = data_storage_data_out; +`else + TxD_data = 0; +`endif TxD_start = 1; tx_toggle = 1; @@ -409,8 +428,10 @@ module remote_access( data_storage_addra_reg = transmit_dsp_status_counter[(RAM_ADDR_BITS-1):0]; if (transmit_dsp_status_counter >= (2**RAM_ADDR_BITS)) begin transmit_dsp_status_done = 1; +`ifdef SYSTEM_HAS_SRAM data_storage_write_enable_reg = 1'bz; data_storage_addra_reg = {(RAM_ADDR_BITS){1'bz}}; +`endif end end end @@ -581,7 +602,9 @@ module remote_access( data_write_timer = data_write_timer - 1; end else begin if (data_write_timer == 1) begin +`ifdef SYSTEM_HAS_SRAM data_storage_write_enable_reg = 0; +`endif data_write_timer = 0; end end @@ -607,9 +630,11 @@ module remote_access( // DSP input data if (dsp_update_counter < (2**RAM_ADDR_BITS)) begin data_storage_remote_enable = 1; +`ifdef SYSTEM_HAS_SRAM data_storage_addra_reg = dsp_update_counter[(RAM_ADDR_BITS-1):0]; data_storage_dina_reg = serial_rx_data_reg; data_storage_write_enable_reg = 1; +`endif data_write_timer = 3; dsp_update_counter = dsp_update_counter + 1; @@ -620,11 +645,15 @@ module remote_access( if (dsp_update_counter >= (2**RAM_ADDR_BITS)) begin next_byte_is_command = 0; +`ifdef SYSTEM_HAS_SRAM data_storage_write_enable_reg = 0; +`endif data_storage_remote_enable = 0; sram_available_reg = 1; +`ifdef SYSTEM_HAS_SRAM data_storage_write_enable_reg = 1'bz; data_storage_addra_reg = {(RAM_ADDR_BITS){1'bz}}; +`endif waiting_on_dsp_processing = 1; transmit_dsp_rx_complete = 1; next_byte_is_command_prev_command = 0; |