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-rw-r--r--fpga/serial/lattice/eb85/main.v4
1 files changed, 3 insertions, 1 deletions
diff --git a/fpga/serial/lattice/eb85/main.v b/fpga/serial/lattice/eb85/main.v
index e736781..58c2a1e 100644
--- a/fpga/serial/lattice/eb85/main.v
+++ b/fpga/serial/lattice/eb85/main.v
@@ -11,6 +11,8 @@ module control_fpga_top
input wire main_12_mhz_clock,
// Guest FPGA interface
+ output wire guest_logic_reset, // Active high guest logic reset signal
+
input wire [3:0] four_bit_output, // Output from the user program to the remote access module
output wire [3:0] four_bit_input, // Input to the user program from the remote access module
input wire [7:0] eight_bit_output, // Output from the user program to the remote access module
@@ -87,7 +89,7 @@ module control_fpga_top
assign lcd_data_in_data = 8'b0; // Disable LCD I/O for now
// Instantiate main remote access module
- remote_access #(RAM_ADDR_BITS) remote_access(.main_fifty_clock(main_50_mhz_clock), .remote_access_4_bit_output(four_bit_output),
+ remote_access #(RAM_ADDR_BITS) remote_access(.main_fifty_clock(main_50_mhz_clock), .user_logic_reset(guest_logic_reset), .remote_access_4_bit_output(four_bit_output),
.remote_access_4_bit_input(four_bit_input), .remote_access_8_bit_output(eight_bit_output),
.remote_access_8_bit_input(eight_bit_input), .remote_access_16_bit_output(sixteen_bit_output),
.remote_access_16_bit_input(sixteen_bit_input),