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* Update copyright datesTimothy Pearson2019-01-241-1/+1
* First pass of logic analyzer functionality (client and FPGA core)Timothy Pearson2014-02-2714-224/+846
* Add ability to hard reset user deviceTimothy Pearson2014-01-132-1/+10
* Add serial I/O to host FPGATimothy Pearson2014-01-122-0/+13
* Max out logic analyzer memoryTimothy Pearson2014-01-125-17/+102
* Add logic analyzer block to control FPGATimothy Pearson2014-01-114-6/+149
* Relayout the GUI to be more in line with expected normsTimothy Pearson2014-01-103-113/+131
* Increase DSP memory sizeTimothy Pearson2014-01-102-1/+7
* Move hardware design files to their correct locationsTimothy Pearson2014-01-097-510/+474
* Add initial GOMC compatible uLab debug system hardware design filesTimothy Pearson2014-01-095-0/+1007