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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// (c) 2014 Timothy Pearson, Raptor Engineering
// Released into the Public Domain
//
//////////////////////////////////////////////////////////////////////////////////
module logic_analyzer_data_storage(
input clka,
input clkb,
input [63:0] dina,
input [63:0] dinb,
input [8:0] addra,
input [8:0] addrb,
input wea,
input web,
output reg [63:0] douta,
output reg [63:0] doutb);
parameter RAM_WIDTH = 64;
// Xilinx specific directive
(* RAM_STYLE="BLOCK" *)
reg [RAM_WIDTH-1:0] data_storage_ram [(2**9)-1:0];
always @(posedge clka) begin
douta <= data_storage_ram[addra];
if (wea) begin
data_storage_ram[addra] <= dina;
douta <= dina;
end
end
always @(posedge clkb) begin
doutb <= data_storage_ram[addrb];
if (web) begin
data_storage_ram[addrb] <= dinb;
doutb <= dinb;
end
end
endmodule
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