fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main_clock_generator.v


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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// (c) 2014 Timothy Pearson, Raptor Engineering
// Released into the Public Domain
//
//////////////////////////////////////////////////////////////////////////////////

module main_clock_generator(
	input clkin,
	output clkout,
	output online);

	assign online = 1'b1;

	BUFG BUFG_inst (
		.O(clkout), // 1-bit output: Clock buffer output
		.I(clkin)  // 1-bit input: Clock buffer input
	);
endmodule