First pass of logic analyzer functionality (client and FPGA core)

9 files changed, 371 insertions, 69 deletions

diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ipcore_dir/lcd_data_storage.xco b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ipcore_dir/lcd_data_storage.xco
new file mode 100644
index 0000000..4f77059
--- /dev/null
+++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ipcore_dir/lcd_data_storage.xco
@@ -0,0 +1,108 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Wed Feb 26 21:06:18 2014
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:blk_mem_gen:7.3
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
+# END Select
+# BEGIN Parameters
+CSET additional_inputs_for_power_estimation=false
+CSET algorithm=Minimum_Area
+CSET assume_synchronous_clk=false
+CSET axi_id_width=4
+CSET axi_slave_type=Memory_Slave
+CSET axi_type=AXI4_Full
+CSET byte_size=9
+CSET coe_file=no_coe_file_loaded
+CSET collision_warnings=ALL
+CSET component_name=lcd_data_storage
+CSET disable_collision_warnings=false
+CSET disable_out_of_range_warnings=false
+CSET ecc=false
+CSET ecctype=No_ECC
+CSET enable_32bit_address=false
+CSET enable_a=Always_Enabled
+CSET enable_b=Always_Enabled
+CSET error_injection_type=Single_Bit_Error_Injection
+CSET fill_remaining_memory_locations=false
+CSET interface_type=Native
+CSET load_init_file=false
+CSET mem_file=no_Mem_file_loaded
+CSET memory_type=True_Dual_Port_RAM
+CSET operating_mode_a=WRITE_FIRST
+CSET operating_mode_b=WRITE_FIRST
+CSET output_reset_value_a=0
+CSET output_reset_value_b=0
+CSET pipeline_stages=0
+CSET port_a_clock=100
+CSET port_a_enable_rate=100
+CSET port_a_write_rate=50
+CSET port_b_clock=100
+CSET port_b_enable_rate=100
+CSET port_b_write_rate=50
+CSET primitive=8kx2
+CSET read_width_a=8
+CSET read_width_b=8
+CSET register_porta_input_of_softecc=false
+CSET register_porta_output_of_memory_core=false
+CSET register_porta_output_of_memory_primitives=false
+CSET register_portb_output_of_memory_core=false
+CSET register_portb_output_of_memory_primitives=false
+CSET register_portb_output_of_softecc=false
+CSET remaining_memory_locations=0
+CSET reset_memory_latch_a=false
+CSET reset_memory_latch_b=false
+CSET reset_priority_a=CE
+CSET reset_priority_b=CE
+CSET reset_type=SYNC
+CSET softecc=false
+CSET use_axi_id=false
+CSET use_bram_block=Stand_Alone
+CSET use_byte_write_enable=false
+CSET use_error_injection_pins=false
+CSET use_regcea_pin=false
+CSET use_regceb_pin=false
+CSET use_rsta_pin=false
+CSET use_rstb_pin=false
+CSET write_depth_a=32
+CSET write_width_a=8
+CSET write_width_b=8
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-19T16:22:25Z
+# END Extra information
+GENERATE
+# CRC: 6d3195aa
diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ipcore_dir/logic_analyzer_data_storage.xco b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ipcore_dir/logic_analyzer_data_storage.xco
new file mode 100644
index 0000000..c47a6a7
--- /dev/null
+++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ipcore_dir/logic_analyzer_data_storage.xco
@@ -0,0 +1,108 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Wed Feb 26 10:22:39 2014
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:blk_mem_gen:7.3
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
+# END Select
+# BEGIN Parameters
+CSET additional_inputs_for_power_estimation=false
+CSET algorithm=Minimum_Area
+CSET assume_synchronous_clk=false
+CSET axi_id_width=4
+CSET axi_slave_type=Memory_Slave
+CSET axi_type=AXI4_Full
+CSET byte_size=9
+CSET coe_file=no_coe_file_loaded
+CSET collision_warnings=ALL
+CSET component_name=logic_analyzer_data_storage
+CSET disable_collision_warnings=false
+CSET disable_out_of_range_warnings=false
+CSET ecc=false
+CSET ecctype=No_ECC
+CSET enable_32bit_address=false
+CSET enable_a=Always_Enabled
+CSET enable_b=Always_Enabled
+CSET error_injection_type=Single_Bit_Error_Injection
+CSET fill_remaining_memory_locations=true
+CSET interface_type=Native
+CSET load_init_file=false
+CSET mem_file=no_Mem_file_loaded
+CSET memory_type=True_Dual_Port_RAM
+CSET operating_mode_a=WRITE_FIRST
+CSET operating_mode_b=WRITE_FIRST
+CSET output_reset_value_a=0
+CSET output_reset_value_b=0
+CSET pipeline_stages=0
+CSET port_a_clock=100
+CSET port_a_enable_rate=100
+CSET port_a_write_rate=50
+CSET port_b_clock=100
+CSET port_b_enable_rate=100
+CSET port_b_write_rate=50
+CSET primitive=8kx2
+CSET read_width_a=64
+CSET read_width_b=64
+CSET register_porta_input_of_softecc=false
+CSET register_porta_output_of_memory_core=false
+CSET register_porta_output_of_memory_primitives=false
+CSET register_portb_output_of_memory_core=false
+CSET register_portb_output_of_memory_primitives=false
+CSET register_portb_output_of_softecc=false
+CSET remaining_memory_locations=AAAAAAAAAAAAAAAA
+CSET reset_memory_latch_a=false
+CSET reset_memory_latch_b=false
+CSET reset_priority_a=CE
+CSET reset_priority_b=CE
+CSET reset_type=SYNC
+CSET softecc=false
+CSET use_axi_id=false
+CSET use_bram_block=Stand_Alone
+CSET use_byte_write_enable=false
+CSET use_error_injection_pins=false
+CSET use_regcea_pin=false
+CSET use_regceb_pin=false
+CSET use_rsta_pin=false
+CSET use_rstb_pin=false
+CSET write_depth_a=2048
+CSET write_width_a=64
+CSET write_width_b=64
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-19T16:22:25Z
+# END Extra information
+GENERATE
+# CRC:  7f171f5
diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/lcd_data_storage.v b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/lcd_data_storage.v
deleted file mode 120000
index 1c1aa6b..0000000
--- a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/lcd_data_storage.v
+++ /dev/null
@@ -1 +0,0 @@
-../../../common/lcd_data_storage.v
\ No newline at end of file
diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_clock_generator.v b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_clock_generator.v
index f13b1e3..05e78dc 100644
--- a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_clock_generator.v
+++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_clock_generator.v
@@ -8,14 +8,23 @@
 
 module logic_analyzer_clock_generator(
 	input clkin,
-	output clkout);
+	output clkout,
+	output online);
+
+	parameter LOGIC_ANALYZER_CLOCK_MULT = 2;
+	parameter LOGIC_ANALYZER_CLOCK_DIV = 2;
 
 	wire clk0;
 	wire clk2x;
-	reg reset;
+	wire clkfx;
+	reg reset = 1'b0;
+	wire locked;
+	wire [7:0] status;
+
+	assign clkout = clkfx;
 
-	assign clkout = clk0;
-// 	assign clkout = clk2x;
+	// Only signal online if the DCM is locked and clkfx is toggling
+	assign online = locked & (~status[2]);
 	
 	// DCM_SP: Digital Clock Manager
 	//         Spartan-6
@@ -24,8 +33,8 @@ module logic_analyzer_clock_generator(
 	DCM_SP #(
 	.CLKDV_DIVIDE(2.0),                   // CLKDV divide value
 						// (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
-	.CLKFX_DIVIDE(1),                     // Divide value on CLKFX outputs - D - (1-32)
-	.CLKFX_MULTIPLY(4),                   // Multiply value on CLKFX outputs - M - (2-32)
+	.CLKFX_DIVIDE(LOGIC_ANALYZER_CLOCK_DIV),                     // Divide value on CLKFX outputs - D - (1-32)
+	.CLKFX_MULTIPLY(LOGIC_ANALYZER_CLOCK_MULT),                   // Multiply value on CLKFX outputs - M - (2-32)
 	.CLKIN_DIVIDE_BY_2("FALSE"),          // CLKIN divide by two (TRUE/FALSE)
 	.CLKIN_PERIOD(10.0),                  // Input clock period specified in nS
 	.CLKOUT_PHASE_SHIFT("NONE"),          // Output phase shift (NONE, FIXED, VARIABLE)
@@ -47,11 +56,11 @@ module logic_analyzer_clock_generator(
 	.CLK2X180(), // 1-bit output: 2X clock frequency, 180 degree clock output
 	.CLK90(),       // 1-bit output: 90 degree clock output
 	.CLKDV(),       // 1-bit output: Divided clock output
-	.CLKFX(),       // 1-bit output: Digital Frequency Synthesizer output (DFS)
+	.CLKFX(clkfx),       // 1-bit output: Digital Frequency Synthesizer output (DFS)
 	.CLKFX180(), // 1-bit output: 180 degree CLKFX output
-	.LOCKED(),     // 1-bit output: DCM_SP Lock Output
+	.LOCKED(locked),     // 1-bit output: DCM_SP Lock Output
 	.PSDONE(),     // 1-bit output: Phase shift done output
-	.STATUS(),     // 8-bit output: DCM_SP status output
+	.STATUS(status),     // 8-bit output: DCM_SP status output
 	.CLKFB(clk0),       // 1-bit input: Clock feedback input
 	.CLKIN(clkin),       // 1-bit input: Clock input
 	.DSSEN(1'b0),       // 1-bit input: Unsupported, specify to GND.
@@ -65,12 +74,11 @@ module logic_analyzer_clock_generator(
 
 	reg [7:0] reset_counter = 8'b00000001;
 	always @(posedge clkin) begin
-		if (reset_counter[7] != 1'b1) begin
+		if (reset_counter[7] == 1'b0) begin
 			reset_counter = reset_counter << 1;
 			reset = 1'b1;
 		end else begin
 			reset = 1'b0;
 		end
 	end
-
 endmodule
diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_data_storage.v b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_data_storage.v
deleted file mode 120000
index 1e8f72d..0000000
--- a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_data_storage.v
+++ /dev/null
@@ -1 +0,0 @@
-../../../common/logic_analyzer_data_storage.v
\ No newline at end of file
diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf
index 8d5384f..1bfce49 100644
--- a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf
+++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main.ucf
@@ -1,42 +1,84 @@
-# (c) 2013 Timothy Pearson, Raptor Engineering
+# (c) 2013-2014 Timothy Pearson, Raptor Engineering
 # Released into the Public Domain
 NET "clk"  LOC = "V10" | IOSTANDARD = "LVCMOS33";
 NET "clk" TNM_NET = clk;
 TIMESPEC TS_clk = PERIOD "clk" 100000 KHz HIGH 50%;
 
+NET "main_clk" TNM_NET = main_clk;
+TIMESPEC TS_main_clk = PERIOD "main_clk" 100000 KHz HIGH 50%;
+
+NET "gpmc_data<0>" OFFSET = OUT 8 ns AFTER "clk";
+NET "gpmc_data<1>" OFFSET = OUT 8 ns AFTER "clk";
+NET "gpmc_data<2>" OFFSET = OUT 8 ns AFTER "clk";
+NET "gpmc_data<3>" OFFSET = OUT 8 ns AFTER "clk";
+NET "gpmc_data<4>" OFFSET = OUT 8 ns AFTER "clk";
+NET "gpmc_data<5>" OFFSET = OUT 8 ns AFTER "clk";
+NET "gpmc_data<6>" OFFSET = OUT 8 ns AFTER "clk";
+NET "gpmc_data<7>" OFFSET = OUT 8 ns AFTER "clk";
+
+NET "gpmc_data<0>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_data<1>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_data<2>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_data<3>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_data<4>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_data<5>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_data<6>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_data<7>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+
+NET "gpmc_address<0>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_address<1>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_address<2>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_address<3>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_address<4>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_address<5>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_address<6>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_address<7>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_address<8>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_address<9>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_address<10>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_address<11>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_address<12>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_address<13>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_address<14>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_address<15>" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+
+NET "gpmc_advn" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_oen" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+NET "gpmc_wen" OFFSET = IN 8 ns VALID 10 ns BEFORE "clk";
+
 #NET "serial_input"  LOC = "T12" | IOSTANDARD = "LVCMOS33";
 #NET "serial_output"  LOC = "M10" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
-NET "gpmc_advn"  LOC = "C5" | IOSTANDARD = "LVCMOS33";
-NET "gpmc_oen"  LOC = "A3" | IOSTANDARD = "LVCMOS33";
-NET "gpmc_wen"  LOC = "A5" | IOSTANDARD = "LVCMOS33";
-
-NET "gpmc_data<0>"  LOC = "A6" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
-NET "gpmc_data<1>"  LOC = "C8" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
-NET "gpmc_data<2>"  LOC = "C9" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
-NET "gpmc_data<3>"  LOC = "A10" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
-NET "gpmc_data<4>"  LOC = "C10" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
-NET "gpmc_data<5>"  LOC = "D9" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
-NET "gpmc_data<6>"  LOC = "D8" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
-NET "gpmc_data<7>"  LOC = "B6" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
-
-NET "gpmc_address<0>" LOC = "A11" | IOSTANDARD = "LVCMOS33";
-NET "gpmc_address<1>" LOC = "F9" | IOSTANDARD = "LVCMOS33";
-NET "gpmc_address<2>" LOC = "A9" | IOSTANDARD = "LVCMOS33";
-NET "gpmc_address<3>" LOC = "A8" | IOSTANDARD = "LVCMOS33";
-NET "gpmc_address<4>" LOC = "A7" | IOSTANDARD = "LVCMOS33";
-NET "gpmc_address<5>" LOC = "C6" | IOSTANDARD = "LVCMOS33";
-NET "gpmc_address<6>" LOC = "A4" | IOSTANDARD = "LVCMOS33";
-NET "gpmc_address<7>" LOC = "A2" | IOSTANDARD = "LVCMOS33";
-NET "gpmc_address<8>" LOC = "B11" | IOSTANDARD = "LVCMOS33";
-NET "gpmc_address<9>" LOC = "G9" | IOSTANDARD = "LVCMOS33";
-NET "gpmc_address<10>" LOC = "B9" | IOSTANDARD = "LVCMOS33";
-NET "gpmc_address<11>" LOC = "B8" | IOSTANDARD = "LVCMOS33";
-NET "gpmc_address<12>" LOC = "C7" | IOSTANDARD = "LVCMOS33";
-NET "gpmc_address<13>" LOC = "D6" | IOSTANDARD = "LVCMOS33";
-NET "gpmc_address<14>" LOC = "B4" | IOSTANDARD = "LVCMOS33";
-NET "gpmc_address<15>" LOC = "B2" | IOSTANDARD = "LVCMOS33";
-
-NET "usermem_wen" LOC = "V16" | IOSTANDARD = "LVCMOS33";
+NET "gpmc_advn"  LOC = "C5" | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_oen"  LOC = "A3" | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_wen"  LOC = "A5" | FLOAT | IOSTANDARD = "LVCMOS33";
+
+NET "gpmc_data<0>"  LOC = "A6" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_data<1>"  LOC = "C8" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_data<2>"  LOC = "C9" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_data<3>"  LOC = "A10" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_data<4>"  LOC = "C10" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_data<5>"  LOC = "D9" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_data<6>"  LOC = "D8" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_data<7>"  LOC = "B6" | SLEW = FAST | FLOAT | IOSTANDARD = "LVCMOS33";
+
+NET "gpmc_address<0>" LOC = "A11" | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_address<1>" LOC = "F9" | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_address<2>" LOC = "A9" | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_address<3>" LOC = "A8" | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_address<4>" LOC = "A7" | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_address<5>" LOC = "C6" | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_address<6>" LOC = "A4" | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_address<7>" LOC = "A2" | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_address<8>" LOC = "B11" | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_address<9>" LOC = "G9" | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_address<10>" LOC = "B9" | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_address<11>" LOC = "B8" | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_address<12>" LOC = "C7" | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_address<13>" LOC = "D6" | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_address<14>" LOC = "B4" | FLOAT | IOSTANDARD = "LVCMOS33";
+NET "gpmc_address<15>" LOC = "B2" | FLOAT | IOSTANDARD = "LVCMOS33";
+
+NET "usermem_wen" LOC = "V16" | PULLUP | IOSTANDARD = "LVCMOS33";
 NET "usermem_wait" LOC = "T18" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
 NET "userproc_start"  LOC = "K16" | SLEW = FAST | IOSTANDARD = "LVCMOS33";
 NET "userproc_done"  LOC = "L13" | IOSTANDARD = "LVCMOS33";
diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main_clock_generator.v b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main_clock_generator.v
new file mode 100644
index 0000000..b867c02
--- /dev/null
+++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/main_clock_generator.v
@@ -0,0 +1,20 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+//
+// (c) 2014 Timothy Pearson, Raptor Engineering
+// Released into the Public Domain
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module main_clock_generator(
+	input clkin,
+	output clkout,
+	output online);
+
+	assign online = 1'b1;
+
+	BUFG BUFG_inst (
+		.O(clkout), // 1-bit output: Clock buffer output
+		.I(clkin)  // 1-bit input: Clock buffer input
+	);
+endmodule
\ No newline at end of file
diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise
index 774cabd..dfb47cf 100644
--- a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise
+++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise
@@ -16,28 +16,44 @@
 
   <files>
     <file xil_pn:name="data_storage.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
-    <file xil_pn:name="lcd_data_storage.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
-    </file>
     <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
-    <file xil_pn:name="logic_analyzer_data_storage.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
+    <file xil_pn:name="logic_analyzer_clock_generator.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="main_clock_generator.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
-    <file xil_pn:name="logic_analyzer_clock_generator.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
+    <file xil_pn:name="verification.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="58"/>
+    </file>
+    <file xil_pn:name="ipcore_dir/logic_analyzer_data_storage.xco" xil_pn:type="FILE_COREGEN">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
+    <file xil_pn:name="ipcore_dir/lcd_data_storage.xco" xil_pn:type="FILE_COREGEN">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+    </file>
+    <file xil_pn:name="ipcore_dir/logic_analyzer_data_storage.xise" xil_pn:type="FILE_COREGENISE">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="ipcore_dir/lcd_data_storage.xise" xil_pn:type="FILE_COREGENISE">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
   </files>
 
   <properties>
@@ -151,7 +167,7 @@
     <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
     <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Implementation Top" xil_pn:value="Module|main" xil_pn:valueState="non-default"/>
@@ -227,7 +243,7 @@
     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="Standard" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
     <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
@@ -269,7 +285,7 @@
     <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="false" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
@@ -281,27 +297,28 @@
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/verification" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.verification" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="work.verification" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.verification" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="10000 ns" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.verification" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="work.verification" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.verification" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
     <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
@@ -349,12 +366,12 @@
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|verification" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="ulab_debug_interface" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="Module|verification" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Module|verification" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/verification.v b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/verification.v
new file mode 120000
index 0000000..2a3bfa8
--- /dev/null
+++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/verification.v
@@ -0,0 +1 @@
+../../../common/verification.v
\ No newline at end of file