| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Update copyright dates | Timothy Pearson | 2019-01-24 | 1 | -1/+1 |
| * | First pass of logic analyzer functionality (client and FPGA core) | Timothy Pearson | 2014-02-27 | 9 | -69/+371 |
| * | Add ability to hard reset user device | Timothy Pearson | 2014-01-13 | 1 | -0/+1 |
| * | Add serial I/O to host FPGA | Timothy Pearson | 2014-01-12 | 1 | -0/+5 |
| * | Max out logic analyzer memory | Timothy Pearson | 2014-01-12 | 3 | -3/+84 |
| * | Add logic analyzer block to control FPGA | Timothy Pearson | 2014-01-11 | 2 | -4/+10 |
| * | Relayout the GUI to be more in line with expected norms | Timothy Pearson | 2014-01-10 | 2 | -112/+114 |
| * | Increase DSP memory size | Timothy Pearson | 2014-01-10 | 1 | -0/+2 |
| * | Move hardware design files to their correct locations | Timothy Pearson | 2014-01-09 | 4 | -510/+4 |
| * | Add initial GOMC compatible uLab debug system hardware design files | Timothy Pearson | 2014-01-09 | 5 | -0/+1007 |
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index : ulab | |
| Donated space for related uLab project | TDE Gitea Workspace |
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