diff options
Diffstat (limited to 'fpga/gpmc/xilinx/numato/spartan6/xc6slx9')
| l--------- | fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_data_storage.v | 1 | ||||
| -rw-r--r-- | fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise | 13 |
2 files changed, 10 insertions, 4 deletions
diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_data_storage.v b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_data_storage.v new file mode 120000 index 0000000..1e8f72d --- /dev/null +++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/logic_analyzer_data_storage.v @@ -0,0 +1 @@ +../../../common/logic_analyzer_data_storage.v
\ No newline at end of file diff --git a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise index 565fe9a..ac7f1e3 100644 --- a/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise +++ b/fpga/gpmc/xilinx/numato/spartan6/xc6slx9/ulab_debug_interface.xise @@ -17,18 +17,22 @@ <files> <file xil_pn:name="data_storage.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> - <association xil_pn:name="Implementation" xil_pn:seqID="2"/> + <association xil_pn:name="Implementation" xil_pn:seqID="3"/> </file> <file xil_pn:name="lcd_data_storage.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> - <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + <association xil_pn:name="Implementation" xil_pn:seqID="2"/> </file> <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" xil_pn:seqID="0"/> </file> <file xil_pn:name="main.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> - <association xil_pn:name="Implementation" xil_pn:seqID="3"/> + <association xil_pn:name="Implementation" xil_pn:seqID="4"/> + </file> + <file xil_pn:name="logic_analyzer_data_storage.v" xil_pn:type="FILE_VERILOG"> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> </file> </files> @@ -93,6 +97,7 @@ <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/> @@ -326,7 +331,7 @@ <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> + <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/applications/xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/> <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> |